Re: 20nm PTM file not working in LTspice
I've explained what I suggest you do. Do you
actually have access to Hspice? If not, forget it and try to use
LTspice, unless you can't find 120nm and 20nm models by any
means.
On 2025-04-04 15:33, Say Die. via
groups.io wrote:
Apologies. It's a bad habit of mine not read instructions
before acting. What should I do now? About My Project I am not
really familiar with HSPICE and the model file is designed for
that APP. And I also don't know how to change the level that
suits LTspice.
?
--
OOO - Own Opinions only
If something is true:
* as far as we know - it's science
*for certain - it's mathematics
*unquestionably - it's religion
|
Re: 20nm PTM file not working in LTspice
On Fri, Apr 4, 2025 at 10:12 AM, Say Die. wrote:
I have uploaded the file also i have notified you guys.
I will fill in the information you forgot to say.
?
The files you uploaded are "FinFETbasedSRAM - 20nm.asc" and "FinFETbasedSRAM.asc".? They are now in the "Temp" folder.? You forgot to put them there, so I fixed that for you.
?
But it is not complete!? You forgot to upload the PTM (model) files.? Without those, your simulations would be useless.? One of your schematics uses early 1970 MOSFETs, which surely are wrong for 20 nm devices.? You gave them ginormous dimensions of 0.18 meters (180000000 nm) by 0.32 meters (120000000 nm), which will be extraordinarily difficult to manufacture.
?
The schematics attempt to load a model file named "180nm_whole.model" but you neglected to upload that, so we can't see where the problem is with your models.? Wasn't that the whole point of this question?
?
I also want to note that you drew your PMOS transistors upside-down.? The Source pin is the one next to the pin for the Gate, and that should be UP (towards the more positive voltage) for your PMOS transistors, not down like you drew them.? You should rotate those symbols twice to get them oriented correctly with Source UP and Drain DOWN.? It might not make a difference (since many MOSFETs are symmetrical), but don't count on it.
?
One of your schematics has a capacitor value of "1micro".? That will give you a 1000 uF capacitance value, because "micro" begins with "m" which is the SPICE multiplier for "milli".
?
Andy
?
|
Re: 20nm PTM file not working in LTspice
Yes, but you uploaded two files instead of a
.ZIP, and didn't upload the model files in it. I looked at your
120nm .ASC. I'm not an expert in IC design, but it looks as
though it might work. But your.TRAN directive is wrong, although
LTspice interprets it sensibly. It should just be .TRAN 120n,
unless you also wanted to set a 1ns maximum time-step, in which
case it should be .TRAN 120n 1n.
On 2025-04-04 15:12, Say Die. via
groups.io wrote:
I have uploaded the file also i have notified you guys.
?
--
OOO - Own Opinions only
If something is true:
* as far as we know - it's science
*for certain - it's mathematics
*unquestionably - it's religion
|
Re: 20nm PTM file not working in LTspice
Apologies. It's a bad habit of mine not read instructions before acting. What should I do now? About My Project I am not really familiar with HSPICE and the model file is designed for that APP. And I also don't know how to change the level that suits LTspice.
?
|
Re: 20nm PTM file not working in LTspice
On Fri, Apr 4, 2025 at 10:12 AM, Say Die. wrote:
I have uploaded the file also i have notified you guys.
But you did not read and follow what John Woodgate wrote!? Neither did you follow the instructions on the group's main webpage!
?
Shame on you for not even trying.
?
Andy
?
|
Re: 20nm PTM file not working in LTspice
There is a special very hot place reserved for
supervisors who set students problems that the supervisor
doesn't know how to solve.?
You might do better to use LTspice, but work
only with the .ASC and models you can find in the group's
archives (the folders with names beginning with 'z...' on the
Files page), together with advice from Andy and others. Or, if
you know, or you supervisor will tell you, which foundry would
make the device you design, you can ask the foundry for 20nm
models.
We can't help with Hspice or any other version
of SPICE.
On 2025-04-04 15:03, Say Die. via
groups.io wrote:
I am just a student and half of the things you said went
bouncer T-T. My HoD told me to make this project because i
attended Semi-conductor training program in SVNIT SURAT. Even he
don't know how to build this circuit and he want me to build and
i am ready ofc, because i love vlsi and designing, but if i know
nothing about it how should i do that. not giving excuses tbh. i
def want to learn that's why i came here. i'll try to send the
file?
?
--
OOO - Own Opinions only
If something is true:
* as far as we know - it's science
*for certain - it's mathematics
*unquestionably - it's religion
|
Re: 20nm PTM file not working in LTspice
On Fri, Apr 4, 2025 at 10:03 AM, Say Die. wrote:
I am just a student and half of the things you said went bouncer T-T. My HoD told me to make this project because i attended Semi-conductor training program in SVNIT SURAT. Even he don't know how to build this circuit and he want me to build and i am ready ofc, because i love vlsi and designing, but if i know nothing about it how should i do that. not giving excuses tbh. i def want to learn that's why i came here. i'll try to send the file?
OK, here is the dumbed-down version of what I wrote:
?
Your model files ("PTM" files) will not work in LTspice.
?
Don't try.? Get the right model files for 20 nm and for the SPICE simulator you intend to use.? If they are LEVEL=72 models, LTspice is not an appropriate simulator because LTspice does not accept LEVEL=72 models.
?
I understand you might be a newbie who is trying to design and simulate circuits about which you know almost nothing.? So I advise you to learn everything you can about MOS circuit design, process scaling, and circuit simulation.? ?There is much that you need to learn.? Anyone can tell you to "go for it", but that might be bad advice especially if both he and you don't know what you are doing, and could get you into a boatload of trouble.
?
If the only models you have are LEVEL=72 models, use the right program with them (HSPICE) and don't try using LTspice with those models.
?
If the only models you have were made for the older 180 nm process, I urge using EXTREME CAUTION with them in an attempt to represent the 20 nm process.? That is not how CMOS scaling works!? There will be different process (PTM) models for each step along the way from 180 nm down to 20 nm, and the 180 nm process files would be wrong for simulating anything designed and built for 20 nm devices.? Anyone who builds those parts (what we call the "FAB") can get you the right model files for the 20 nm process.? Now maybe that is what they did already.? ?Scaling down from 180 nm to 20 nm requires both changing the sizes of the transistors (which is usually specified on the schematics), and changing the SPICE model files; both steps need to be done.? I want to make sure you understand that.
?
By the way, please go easy on the abbreviations.? Not everyone understands all the acronyms you used.
?
Andy
?
?
|
Re: 20nm PTM file not working in LTspice
I have uploaded the file also i have notified you guys.
?
|
Re: 20nm PTM file not working in LTspice
I am just a student and half of the things you said went bouncer T-T. My HoD told me to make this project because i attended Semi-conductor training program in SVNIT SURAT. Even he don't know how to build this circuit and he want me to build and i am ready ofc, because i love vlsi and designing, but if i know nothing about it how should i do that. not giving excuses tbh. i def want to learn that's why i came here. i'll try to send the file?
?
|
Re: 20nm PTM file not working in LTspice
On Fri, Apr 4, 2025 at 09:03 AM, Say Die. wrote:
my 180nm file ran properly but when i tried for 20nm it's not working although i changed W/L ratio from L=0.18 ,W= 0.64 to L= 0.02 to W= 0.3.??
Note that simply scaling the dimensions as you did, does not get you from a 180 nm process to a 20 nm process.
?
There are significant changes necessary in the model (PTM) files themselves.? You should use only the models that were specifically made for your 20 nm FAB process.? Don't try using 180 nm process models to "fake it" for devices scaled down to 20 nm.? Well, I guess you could for your Extremely Preliminary simulations with the wrong process, but do not depend on their simulation results without getting the right process models for your new FAB process.
?
Andy
?
|
Re: 20nm PTM file not working in LTspice
On Fri, Apr 4, 2025 at 09:26 AM, Say Die. wrote:
Did you read the advice already given?
?
?
Please go back to the starting gate and begin again.? Read the instructions first.
?
?
|
Re: 20nm PTM file not working in LTspice
On Fri, Apr 4, 2025 at 09:03 AM, <siddhugoad@...> wrote:
I am trying to build 6T SRAM using 20nm but when i run the simulation i am having the errors saying parameter level = 72 and also other bunch of errors.
LTspice does not support "LEVEL=72" MOSFET models.? If those are the only models you have for your 20 nm devices, then you will need to use another SPICE program with it.? Probably that is HSPICE.
?
LTspice accepts (among others) LEVEL=9, 14, 49, 54, and 73, but not 72.? You can find the LEVEL number by carefully examining the .MODEL statements.
?
If I remember correctly, other users in this group may have used 45 nm and 20 nm models previously with LTspice, so models might exist for your devices that can be used with LTspice.? Even so, caution is called for because some of those model types are very uncommon and there are things that may not work properly, even if you get them working.? In the meantime, abandon any hope of using your LEVEL=72 models with LTspice.? It simply will not work.
my 180nm file ran properly but when i tried for 20nm it's not working although i changed W/L ratio from L=0.18 ,W= 0.64 to L= 0.02 to W= 0.3.??
Those are extraordinary incorrect W and L values!? Who would make a MOSFET that is 0.18 meters by 0.64 meters!? ?Surely those must be incorrect.? Did you forget to add the units?? (Probably missing the "u" unit multiplier.)
?
Now there is a catch to what I just said.? There is a SPICE program that accepts values such as those, because it allows non-MKS units (.OPTIONS SCALM=<val>) - which IMO is a Really Bad Idea.? Anyway, if you have models that were made for that SPICE program, it would be unwise to try to use those models with any SPICE program other than the one they were made for.
?
?
What should i do ?
I? suggest that you consider purchasing that SPICE program and using it for these simulations, and don't try to run them in LTspice nor any other SPICE program besides the one they were made for.? Those models are much too program-specific.? Note it will cost you dearly to buy that program.? That is life.? Maybe your employer already has that program.? Do not consider stealing it or getting a free "hack" of that program (HSPICE).? It is not legal.
?
Andy
?
|
Re: 20nm PTM file not working in LTspice
Read the message! BOLD TYPE
On 2025-04-04 14:25, Say Die. via
groups.io wrote:
How should I upload ?
We can't help much unless you let us
see more of what you are doing. Upload your .ASC file
AND all the other files required to run the simulation,
but not .RAW? and .LOG files or pictures,? in a ZIP
archive to Files => Temp.
Go to the web page: /g/LTspice/topics.
Click on Files in the list on the left. Then click on
Temp. Then click on New Upload in the blue box at top
left. Click on Upload File in the drop-down menu. Then
send a message to tell us that you did that.
On 2025-04-04 13:59, siddhugoad via wrote:
I am trying to build 6T SRAM using 20nm but when i
run the simulation i am having the errors saying
parameter level = 72 and also other bunch of errors.
my 180nm file ran properly but when i tried for 20nm
it's not working although i changed W/L ratio from
L=0.18 ,W= 0.64 to L= 0.02 to W= 0.3.??
What should i do ?
--
OOO - Own Opinions only If something is true: * as far as
we know - it's science *for certain - it's mathematics
*unquestionably - it's religion
--
OOO - Own Opinions only
If something is true:
* as far as we know - it's science
*for certain - it's mathematics
*unquestionably - it's religion
|
Re: 20nm PTM file not working in LTspice
toggle quoted message
Show quoted text
We can't help much unless you let us see more
of what you are doing. Upload your .ASC file AND all the other
files required to run the simulation, but not .RAW? and .LOG
files or pictures,? in a ZIP archive to Files => Temp.
Go to the web page: /g/LTspice/topics. Click on
Files in the list on the left. Then click on Temp. Then click on
New Upload in the blue box at top left. Click on Upload File in
the drop-down menu. Then send a message to tell us that you did
that.
On 2025-04-04 13:59, siddhugoad via
wrote:
I am trying to build 6T SRAM using 20nm but when i run the
simulation i am having the errors saying parameter level = 72
and also other bunch of errors.
my 180nm file ran properly but when i tried for 20nm it's not
working although i changed W/L ratio from L=0.18 ,W= 0.64 to L=
0.02 to W= 0.3.??
What should i do ?
--
OOO - Own Opinions only
If something is true:
* as far as we know - it's science
*for certain - it's mathematics
*unquestionably - it's religion
|
Re: 20nm PTM file not working in LTspice
We can't help much unless you let us see more
of what you are doing. Upload your .ASC file AND all the other
files required to run the simulation, but not .RAW? and .LOG
files or pictures,? in a ZIP archive to Files => Temp.
Go to the web page: /g/LTspice/topics. Click on
Files in the list on the left. Then click on Temp. Then click on
New Upload in the blue box at top left. Click on Upload File in
the drop-down menu. Then send a message to tell us that you did
that.
On 2025-04-04 13:59, siddhugoad via
groups.io wrote:
I am trying to build 6T SRAM using 20nm but when i run the
simulation i am having the errors saying parameter level = 72
and also other bunch of errors.
my 180nm file ran properly but when i tried for 20nm it's not
working although i changed W/L ratio from L=0.18 ,W= 0.64 to L=
0.02 to W= 0.3.??
What should i do ?
--
OOO - Own Opinions only
If something is true:
* as far as we know - it's science
*for certain - it's mathematics
*unquestionably - it's religion
|
20nm PTM file not working in LTspice
I am trying to build 6T SRAM using 20nm but when i run the simulation i am having the errors saying parameter level = 72 and also other bunch of errors.
my 180nm file ran properly but when i tried for 20nm it's not working although i changed W/L ratio from L=0.18 ,W= 0.64 to L= 0.02 to W= 0.3.??
What should i do ?
|
Re: Switching Speed of a BJT
On 03/04/2025 10:34, Tony Casey wrote:
On 03/04/2025 09:26, jacfev via
groups.io wrote:
My question
is multiple:
1. What are the influential spice parameters that optimize the
switching speed?
To my knowledge, it's mainly Bf that seems to be the most
important for increasing the switching speed, which I vary like
this:
.step param X LIST 100 150 200 250 300
.model myModel AKO: 2N2222 NPN (Bf={X})
2. What measurement (equation) can be used to measure the speed?
3. What circuit should I use to compare the switching speed
results as a function of the influential parameter?
This is not such a simple question. What are your parameters for
switching speed? Presumably rise and fall times? How about delays
times? You can still have fast rise and fall times, but with a
significant delay time if the transistor is driven into
saturation.
I would say that Bf is not one of the most influential parameters
for speed. More important are the internal capacitances: Cje and
Cjc, and transit times: Tf and Tr. Tr sets the reverse recovery
time, i.e. charge storage in the base region on switch off - this
is critical in saturated BJT switching circuits.
To assess the speed, you need to .MEAS the rise and fall times at
the output, and the turn-on and turn-off delay times referenced to
the input source waveform.
Testjig uploaded to Files > Temp: BJT_Switching_Speed_Jig.zip
--
Regards,
Tony
|
Re: Switching Speed of a BJT
I agree with Tony. If Bf is found to affect
switching speed, we need to see the test circuit .ASC that you
are using, because it's probably not the optimum.
On 2025-04-03 09:34, Tony Casey wrote:
On 03/04/2025 09:26, jacfev via
groups.io wrote:
My question
is multiple:
1. What are the influential spice parameters that optimize the
switching speed?
To my knowledge, it's mainly Bf that seems to be the most
important for increasing the switching speed, which I vary like
this:
.step param X LIST 100 150 200 250 300
.model myModel AKO: 2N2222 NPN (Bf={X})
2. What measurement (equation) can be used to measure the speed?
3. What circuit should I use to compare the switching speed
results as a function of the influential parameter?
This is not such a simple question. What are your parameters for
switching speed? Presumably rise and fall times? How about delays
times? You can still have fast rise and fall times, but with a
significant delay time if the transistor is driven into
saturation.
I would say that Bf is not one of the most influential parameters
for speed. More important are the internal capacitances: Cje and
Cjc, and transit times: Tf and Tr. Tr sets the reverse recovery
time, i.e. charge storage in the base region on switch off - this
is critical in saturated BJT switching circuits.
To assess the speed, you need to .MEAS the rise and fall times at
the output, and the turn-on and turn-off delay times referenced to
the input source waveform.
--
Regards,
Tony
--
OOO - Own Opinions only
If something is true:
* as far as we know - it's science
*for certain - it's mathematics
*unquestionably - it's religion
|
On 03/04/2025 09:55, eewiz via
groups.io wrote:
Gentlemen, those CD4x and 74HC libraries have two required
values that appear on a symbol's SpiceModel line.
ctrl-right-click a logic symbol to alter its SpiceModel line.
By default the two values are the nodes "VDD" and "0".
Creating a 12V power supply for CD4x logic and naming its
output node VDD works out-of-the-box.
But assume for example, you already have a V-24 node and a
V-12 node that could power the logic.
Change the logic symbol's default SpiceModel value from "VDD
0" to "V-12 V-24".
This sets logic outputs to be V(V-12)=logic-high and
V(V-24)=logic-low, instead of VDD/0.
?
In either case the difference across the power pins is 12
volts, -12 to -24 volts or 12 to 0 volts has the same 12 volt
difference.
To power the internal logic from 12 volts, change the
symbol's default SpiceLine (not SpiceModel) value from VDD=5 to
VDD=12.
The SpiceLine VDD=x value sets the model's power-pin voltage
and can be anything like VDD=2.3 or 3.5, 6, 12 etc...
The three SpiceLine values control functions within the logic
like, prop-delay, output drive, slew rate, etc...
The SpiceLine SPEED=1.0 and TRIPDT=5e-9 are defaulted for the
logic family.
?
Changing the VDD=x value affects the speed of a given device.
(i.e. CD4x is much faster at 15V than it is at 5V)
The SpiceLine SPEED=1.0 value is relative.
To model CD4x-like logic at 12 volts that is 10 times faster
than normal CD4x logic, change the SpiceLine SPEED=1.0 value to
SPEED=10.
This is not quite correct. The CD4000 parts do have the internal
"VDD" supply node, but in the 74HC parts, it is "VCC".
--
Regards,
Tony
|
Re: Switching Speed of a BJT
On 03/04/2025 09:26, jacfev via
groups.io wrote:
My question is
multiple:
1. What are the influential spice parameters that optimize the
switching speed?
To my knowledge, it's mainly Bf that seems to be the most
important for increasing the switching speed, which I vary like
this:
.step param X LIST 100 150 200 250 300
.model myModel AKO: 2N2222 NPN (Bf={X})
2. What measurement (equation) can be used to measure the speed?
3. What circuit should I use to compare the switching speed
results as a function of the influential parameter?
This is not such a simple question. What are your parameters for
switching speed? Presumably rise and fall times? How about delays
times? You can still have fast rise and fall times, but with a
significant delay time if the transistor is driven into saturation.
I would say that Bf is not one of the most influential parameters
for speed. More important are the internal capacitances: Cje and
Cjc, and transit times: Tf and Tr. Tr sets the reverse recovery
time, i.e. charge storage in the base region on switch off - this is
critical in saturated BJT switching circuits.
To assess the speed, you need to .MEAS the rise and fall times at
the output, and the turn-on and turn-off delay times referenced to
the input source waveform.
--
Regards,
Tony
|
John Woodgate
Tony Casey