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Hello

I see that it's a subcircuit. In this case, if you want to use the symbol for PMOS, then Ctrl-right-click on it, rename MP to X and then rename PMOS to IRLML5103. Of course, having the subcircuit's text as a SPICE directive on the schematic or in a custom library is necessary.

Merry Christmas to you, too

Vlad

How can I get model of c828 trasistor. Please help.

I have managed to locate a CD4000.lib zip file - I have attempted to download an example which has the 'include CD4000.lib' listed on the schematic, however, I keep getting the following error:

"Could not open include file "CD4000.lib"

Any ideas?

I thought a Yahoo ID *was* a Yahoo account.

Yahoo has always retired accounts that go unused for just a few months.
(At most 6.) I know this from personal experience.

But do they cancel Yahoo identities? I don't think any other form of
'Yahoo account' is required.

Thanks Andy for your reply!

You are totally right; the step size is reduced with a factor of 8, when the non-linear equations do not converge. But that is not the only control method. The local truncation error of the numerical integrations is evaluated in each time step. Depending on that error the step-size get a smooth shape.

Meanwhile I found Mikes statements to the modified trap as well. Too bad, there is no information about the way it works. I don't think it is a complete proprietary method, because as far as I know it's also used in Spice Opus (and maybe other Spice-like programs?). It was also explained by A. Brambilla in http://bit.ly/1dNhwgl.

Another thing is, that one need a lot of research to invent a complete new time integration method. Gear's method for instance is studied in lots of papers, before it was used in software program. I have written a new topic in order to find more information. If you are interested, you can follow the discussion in: http://groups.yahoo.com/neo/groups/LTspice/conversations/messages/72509

Hello Andy

And thank you for the reply. If you're worried about not being in your area of expertise, what can I say? I''' be brave and try to address your notes in the order you posted them.

> Why is the Gain of the first VCCS (G1) so very low?

The upsampler, as it is now, uses a SW controlled by V(0.3), but I also tried removing SW (replaced by the nearby R17) and using a B-source with the expression V(0.3)*V(108). You probably know that they tend to get slower as the processed values are higher so, given that with a unity gain at the input I could have gotten some hundred volts at the resampler (with the current input) and could have gotten even higher depending on the input levels, I decided to use the (M*R)**-N gain at the input knowing that it would, eventually, have had to be used somewhere along the way. The schematic you see is what is left after testing. After changing the upsampler I was left with the small gain at the input which made no difference to the output so I just left it there.

Still, you have a point there with the V <-> nV (MV <-> V in the case of unity gain input), so that may be one of the causes, but I suspect not because I also tried using integrators with 1/M/R gain, each stage, but didn't get any improvement. I haven't fiddled with tolerences, though, I will later today.

> Current source I1 looks odd

Since .AC through a S&H is not possible and since I try not to use voltage sources otherwise than grounded (convergence issues, as by the book), I used Rout=1 for the S&H (unlike its cousins, it defaults to 1k) and used I1 with only "AC 1" for .AC analysis. However, .AC works just fine (it needs a minor change to the current schematic to work).

> V4 and V5 have "zero" fall times

Yes, I know about the default times and that's the reason they are there as such: the clock sources are only needed for their rise times; fall times and pulse width have no influence (other than messing with the time-step). So, forcing only tr and period makes the source give the needed rise time while relaxing tf and ton, thus achieving the same results only a bit faster. In more complicated schematics this can be quite the time saver.

> The time-delay elements in the lower string are curious

They're intended. In order to turn it into an integrator and make it as the simplest approach, I used the tline as inverting output feeding the - input.

> Have you considered using B-elements as the delay lines

Yes, various combinations, with or without custom functions (like comb(x) {v(x)-delay(v(x),tcomb)}) and they seemed to behave worse. Maybe it's because of the nV <> V difference? I'll have to try this one today, too.

> You may need to specify a Maximum Timestep.

I even had patience for usec timesteps :-) , no change, though it's true I, too, would've expected a more "detailed" clock output with no timestep imposed.

> How did you get the "COUNTER" behavioral element to use a gate-type symbol?

You simply rename INV to COUNTER. No, it doesn't matter :-)

> The error log has several "singular matrix" flags

I don't know why, node q is the output of the first integrator, node o is the output of the last one (the output of the filter). If it complains about them, why not complain about the other 6? Is it only because they're named? Apparently not since deleting q (for example) will make LTspice complain about N025 (as I have it) and o. The simulation runs, though, as you can see... No idea what other meaning it has.

At the end, it seems there are two things to try: the nV <> V difference and the reltol, abstol & co. I'll test these later and see what comes out of it.

Thank you for the answers.

Vlad

Yahoo has always retired accounts that go unused for just a few months.
?(At most 6.) ?I know this from personal experience.

Yes? I can appreciate there are various? sources of inaccuracy? Those? I have seen are not even close to a narrow band response.for example 1.5 MHz at 14MHz, similar bandwidth % at 1kHz

If someone can send me the set-up details to show what is possible for a simple square-wave it would be enormously helpful?