Re: constructing opamp models
--- In LTspice@..., "Dale <dchishol@c...>" <dchishol@c...> wrote: --- In LTspice@..., "oztek_jtg <jgraham@o...>"
<jgraham@o...> wrote:
What's the best way of creating an opamp model if the manufacturer
does not have a spice model for it?
Thanx,
-Jon If you're employed as a design engineer, sometimes you can get a
vendor to develop a model on request.
Mere mortals have to use what's available on published data sheets
and try to fit it into the component values of standard macromodel
topologies. Several published works deal with this. - - - > SNIP < - - - If anybody knows of more recent works than what I previously cited, I am definitely interested in learning about them!! I've been putting together an EXCEL spreadsheet that takes a couple dozen values from the datasheet & spits out a macromodel text file, but it's not yet ready for general distribution. Dale
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Re: constructing opamp models
--- In LTspice@..., "oztek_jtg <jgraham@o...>" <jgraham@o...> wrote: What's the best way of creating an opamp model if the manufacturer
does not have a spice model for it?
Thanx,
-Jon If you're employed as a design engineer, sometimes you can get a vendor to develop a model on request. Mere mortals have to use what's available on published data sheets and try to fit it into the component values of standard macromodel topologies. Several published works deal with this. The seminal paper is useful and readable, but later works are much better: 'Macromodeling of Integrated Circuit Operational Amplifiers', (Boyle et al), IEEE Journal of Solid State Circuits vol SC-9 (Dec 1974) Copy it from the library of any University near you that has an Engineering school, or decent Physics department. (In this area, that's Washington Univ or Univ of Mo - St Louis; even the St Louis Public Library has a LOT(!!) of the IEEE pubs on microform.) Walk in like you own the place and ask for help finding the right shelves - no librarian has ever thrown out anybody who was behaving himself. Three manufacturers have published app notes that do a pretty good job of linking data sheets to model parameters via equations: 'SPICE-Compatible Op Amp Macro-Models', (Alexander & Bowers), Analog Devices Application Note AN-138 (1990) (originally published as 'Designer's Guide to SPICE-Compatible Macromodels', in Electronic Design News (EDN), vol 35 no 4, Feb 15 1990 (Part 1) & no 5, Mar 1 1990 (Part 2)) 'Using the LTC Op Amp Macromodels', (Jung), Linear Technology Application Note 48 (1991) 'Development of an Extensive SPICE Macromodel for "Current-Feedback" Amplifiers', National Semiconductor Application Note 840 (Jul 1992) These are all available as PDF files from the respective vendors web sites, and other places on the web. Don't dismiss the National paper because it says "Current-Feedback" - most of what it says applies to modeling ANY op-amp. Along the same lines, you might look at: 'A Comprehensive Simulation Macromodel for "Current-Feedback" Operational Amplifiers', (Bowers), IEE Procedings vol 137 pg 137-145 (Apr 1990) Note that this is published by the U.K. IEE, not the American IEEE! Dale
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constructing opamp models
What's the best way of creating an opamp model if the manufacturer
does not have a spice model for it?
Thanx,
-Jon
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Re: Can't open library file.
Is the file really called "MYLIBRARY1.LIB" or "MYLIBRARY1.LIB.txt"? I turn off "Hide file extension for known file types" in Explorer=>Tools=>Folder Options=>View "MYLIBRARY1.LIB" needs to be the full name of the file and it must be an ASCII file. --Mike --- "bunnyblues2001 <bunnyblues2001@...>" <bunnyblues2001@...> wrote: OK where did I go wrong, I'm getting - Could not
open include file
"MYLIBRARY1.LIB"
I copied the switch out of help, and the library is
in the sub
directory.
MYLIBRARY1.lib
*SYM=CSW
.MODEL CSWITCH1 1 2
W1 out 0 Vsense CSWITCH1
Vsense a b 0.
.model CSWITCH1 CSW(Ron=.1 Roff=1Meg Vt=0 Vh=-.5)
.ENDS
Version 4
SHEET 1 892 692
WIRE 448 384 448 448
WIRE 448 528 448 560
WIRE 448 560 208 560
WIRE 208 560 208 384
WIRE 208 560 208 576
WIRE 208 304 448 304
FLAG 208 576 0
SYMBOL C:\PROGRAM\
FILES\LTC\SWCADIII\lib\sym\voltage 208 288 R0
WINDOW 123 24 132 Left 0
WINDOW 39 24 160 Left 0
WINDOW 0 42 52 Left 0
SYMATTR Value2 AC 20
SYMATTR SpiceLine Rser=1
SYMATTR InstName V1
SYMATTR Value SINE(0 20 5000)
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\csw
448 304 R0
WINDOW 0 55 20 Left 0
SYMATTR InstName W1
SYMATTR Value CSWITCH1
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\res
432 432 R0
SYMATTR InstName R1
SYMATTR Value 10
TEXT 488 560 Left 0 !.include MYLIBRARY1.lib
TEXT 174 600 Left 0 !.tran 0 .1 .001 .001
* C:\Program Files\LTC\schematics\current.asc
V1 N002 0 SINE(0 20 5000) AC 20 Rser=1
W1 N002 N001 CSWITCH1
R1 N001 0 10
.include MYLIBRARY1.lib
.tran 0 .1 .001 .001
.backanno
.end
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OK where did I go wrong, I'm getting - Could not open include file
"MYLIBRARY1.LIB"
I copied the switch out of help, and the library is in the sub
directory.
MYLIBRARY1.lib
*SYM=CSW
.MODEL CSWITCH1 1 2
W1 out 0 Vsense CSWITCH1
Vsense a b 0.
.model CSWITCH1 CSW(Ron=.1 Roff=1Meg Vt=0 Vh=-.5)
.ENDS
Version 4
SHEET 1 892 692
WIRE 448 384 448 448
WIRE 448 528 448 560
WIRE 448 560 208 560
WIRE 208 560 208 384
WIRE 208 560 208 576
WIRE 208 304 448 304
FLAG 208 576 0
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\voltage 208 288 R0
WINDOW 123 24 132 Left 0
WINDOW 39 24 160 Left 0
WINDOW 0 42 52 Left 0
SYMATTR Value2 AC 20
SYMATTR SpiceLine Rser=1
SYMATTR InstName V1
SYMATTR Value SINE(0 20 5000)
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\csw 448 304 R0
WINDOW 0 55 20 Left 0
SYMATTR InstName W1
SYMATTR Value CSWITCH1
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\res 432 432 R0
SYMATTR InstName R1
SYMATTR Value 10
TEXT 488 560 Left 0 !.include MYLIBRARY1.lib
TEXT 174 600 Left 0 !.tran 0 .1 .001 .001
* C:\Program Files\LTC\schematics\current.asc
V1 N002 0 SINE(0 20 5000) AC 20 Rser=1
W1 N002 N001 CSWITCH1
R1 N001 0 10
.include MYLIBRARY1.lib
.tran 0 .1 .001 .001
.backanno
.end
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Re: New User - A question & suggestion
--- In LTspice@..., "bolocolombo <colombobolo@h...>" <colombobolo@h...> wrote: I recently discovered LTSpice and I love the program.
My question is the following:
I wish to modify the model parameters of say, the NPN bipolar
transistor, so as to see the impact of various parameters on ECL gate delay. I know how to do this on the netlist, but I cannot see how I can do this from the schematic entry - when I right click on the NPN, where can I modify things like BF, Is, etc.? I have not found anything about this in the help. Did I miss it?
Hello Bolo, I remember one method to do something like that. So at least the .STEP command allows access to the transistor's parameters. Example syntax: .STEP NPN QPMBT3904(bf) list 100, 250, 500 The simulation would run with bf=100, 250 and 500. The basic example is in the file "stepmodelparam.asc" in the "educational"-directory of SwitcherCADIII. I have attached another example that uses a .INCLUDE statement for the transistor library, because it doesn't use a model from the standard.bjt library. I think this is exactly the case you have with your ECL-gate library. Put the library file and the schematic file in the same directory. I would be ecstatic if we could plot/display S-parameters within
LTSpice, in a Smith Chart and Bode format. I managed to plot them, but one needs to build this fictitious circuit around the real circuit in order to extract the S-parameters. And then one needs to write out huge expressions to plot H21, MAG/MSG, and U... If Linear Technology is
interested in the RF market, it might make sense to add S-parameter
tools down the line. What's about to hide these long expressions in B-sources? I am interested in the S-Parameter simulations you did. Can you post some sample files with an explanation? Best Regards Helmut Circuit file "curvetrace1.asc" ----------------------------- Version 4 SHEET 1 2376 1528 WIRE 1984 1376 1984 1296 WIRE 1984 1200 1984 1152 WIRE 1984 1152 2160 1152 WIRE 2160 1152 2160 1216 WIRE 2160 1296 2160 1376 WIRE 1808 1280 1808 1248 WIRE 1808 1248 1920 1248 WIRE 1808 1360 1808 1376 FLAG 2160 1376 GND FLAG 1984 1376 GND FLAG 1808 1376 GND SYMBOL NPN 1920 1200 R0 SYMATTR InstName Q1 SYMATTR Value QPMBT3904 SYMBOL voltage 2160 1200 R0 SYMATTR InstName V1 SYMATTR Value 0. SYMBOL CURRENT 1808 1360 M180 WINDOW 0 24 88 Left 0 WINDOW 3 24 0 Left 0 SYMATTR InstName I1 SYMATTR Value 0. TEXT 1768 1440 Left 0 !.dc V1 0 15 10m I1 50u 100u 50u TEXT 1416 1512 Left 0 ;This example schematic is supplied for informational/educational purposes only. TEXT 1696 1080 Left 0 !.step NPN QPMBT3904(bf) list 100, 1000 TEXT 1696 1120 Left 0 !.include philips.lib Library "philips.lib" ----------------------- * .MODEL QPMBT3904 NPN( + IS=4.639E-15 + NF=0.9995 + ISE=2.091E-14 + NE=1.6 + BF=160.1 + IKF=0.12 + VAF=98.69 + NR=1.001 + ISC=3.257E-12 + NC=1.394 + BR=5.944 + IKR=0.06 + VAR=19.29 + RB=1 + IRB=1E-06 + RBM=1 + RE=0.3614 + RC=1.755 + XTB=0 + EG=1.11 + XTI=3 + CJE=5.631E-12 + VJE=0.7002 + MJE=0.3385 + TF=3.001E-10 + XTF=27 + VTF=1.461 + ITF=0.2723 + PTF=0 + CJC=4.949E-12 + VJC=0.5969 + MJC=0.1928 + XCJC=0.864 + TR=9.4E-8 + CJS=0 + VJS=0.75 + MJS=0.333 + FC=0.5582 ) *
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New User - A question & suggestion
I recently discovered LTSpice and I love the program.
My question is the following:
I wish to modify the model parameters of say, the NPN bipolar
transistor, so as to see the impact of various parameters on ECL gate
delay. I know how to do this on the netlist, but I cannot see how I can
do this from the schematic entry - when I right click on the NPN, where
can I modify things like BF, Is, etc.? I have not found anything about
this in the help. Did I miss it?
Suggestion:
I appreciate LTSPice is "free", so one can only do so much work on it
in terms of filling requests... But here is mine anyway.
I would be ecstatic if we could plot/display S-parameters within
LTSpice, in a Smith Chart and Bode format. I managed to plot them, but
one needs to build this fictitious circuit around the real circuit in
order to extract the S-parameters. And then one needs to write out huge
expressions to plot H21, MAG/MSG, and U... If Linear Technology is
interested in the RF market, it might make sense to add S-parameter
tools down the line.
Being able to export data w/o the Ltutil.exe would be good too.
Thanks for a great tool.
Cheers!
Bolo
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Re: how to use cell attributes to bind a symbol to a subcircuit
I need a method to bind schematics to cell and
block symbols that uses the symbol attributes,
so that instantiating and placing a symbol
causes that symbol's definition to be included
as a subcircuit in the netlist[...] You can do this if the symbol is modeled with a subcircuit. It's described in one of the downloads of this group and now also in the help section Schematic Capture=>Creating New Symbols=>Adding Attributes: There is a special combination of attributes that will cause a required library to be automatically included in every schematic that uses the symbol: Prefix: X SpiceModel: <name of file including the spicemodel> Value: <What ever you want vis. on the schematic> Value2: <The value as you want in the netlist> If the device is modeled with a .model card, then you need to put the .model statement in the appropriate standard.* file. --Mike __________________________________________________ Do you Yahoo!? Yahoo! Shopping - Send Flowers for Valentine's Day
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how to use cell attributes to bind a symbol to a subcircuit
I need a method to bind schematics to cell and block symbols that uses the
symbol attributes, so that instantiating and placing a symbol causes that
symbol's definition to be included as a subcircuit in the netlist. This
needs to work
a) when the symbol and schematic have the same name (albeit with differing
extensions),
b) when the symbol and schematic have different names (e.g., "XXX.asy"
bound to "simplified_XXX.asc"), and
c) when a generic symbol is bound after placement to a specific
differently-named schematic (e.g., when binding different power supply
designs into a common test framework).
File hierarchy location of the files for the symbols and schematics is not
important, as long as they are not placed under the SCad3 Program Files
hierarchy. (They aren't LTC's.) The solution could require that all of the
symbols and schematics files be in the same folder, probably the folder on
which SCad3 is focussed. Or the solution could require replicating a lib
hierarchy under the folder on which SCad3 is focussed. Or ???
Requiring the instantiating user to know the correlation between symbol and
schematic and add a .lib statement for each such is unacceptable, just as it
would be were a .lib to be needed for each LT part and discrete that is
added to a schematic. Besides, adding a .lib statement does not solve the
problem of binding a symbol with one name to an instance with a different
name, as occurs in the LT-provided symbols (e.g., CNY17-3.asy binding to
CNY17.sub as in last example below)
Placing a pre-bound symbol should be adequate when the symbol has a fixed
binding to a subcircuit netlist. Placing an unbound symbol and setting one
or two of the symbol instance's attributes to the name of the netlist should
be adequate for binding a generic symbol to one of a set of equivalent
netlists. (Note that a .lib cannot accomplish this, particularly when two
identical generic symbols in the schematic are bound to different instance
values, as occurs regularly with generic symbols for discretes.)
I've tried binding the schematic to the symbol definition and/or to the
symbol instance via the SpiceModel attribute. I've also tried binding it
via the SpiceLine2 attribute by putting a "\n.lib " prefix before the
schematic name, hoping that this would cause SCad3 to treat this as a
separate hidden .lib declaration.
Neither of these approaches works. Nor does removing the represented cell's
or block's name, which is otherwise appended to the constructed SPICE line
after the SpiceModel field. (Incidentally, cell's _do_ need names, so
removing the name would not be an acceptable method either. But it was
worth trying.:)
Has anyone solved this problem? Does anyone have any suggestions? Is there
a methodology for adding bogus pins to the symbol to cause the SPICE parse
of the constructed SpiceLine to work?
Mike?
Helmut?
Others?
Two example symbols and schematics follow:
**attempt to use SpiceModel attribute**
==============diode bridge symbol================
Version 4
SymbolType CELL
LINE Normal -20 16 -20 -16
LINE Normal -44 16 -44 -16
LINE Normal -44 -16 -20 0
LINE Normal -44 16 -20 0
LINE Normal -64 0 -44 0
LINE Normal -20 0 0 0
LINE Normal 60 64 60 32
LINE Normal 36 64 36 32
LINE Normal 36 32 60 48
LINE Normal 36 64 60 48
LINE Normal 0 48 36 48
LINE Normal 60 48 80 48
LINE Normal 60 16 60 -16
LINE Normal 36 16 36 -16
LINE Normal 36 -16 60 0
LINE Normal 36 16 60 0
LINE Normal 16 0 36 0
LINE Normal 60 0 80 0
LINE Normal -20 -32 -20 -64
LINE Normal -44 -32 -44 -64
LINE Normal -44 -64 -20 -48
LINE Normal -44 -32 -20 -48
LINE Normal -64 -48 -44 -48
LINE Normal -20 -48 16 -48
LINE Normal 16 -48 16 -48
LINE Normal 16 0 16 -48
LINE Normal 80 -48 16 -48
LINE Normal 0 48 0 0
LINE Normal -64 48 0 48
RECTANGLE Normal 80 72 -64 -71
TEXT -16 -96 Left 0 BRW40
WINDOW 0 -51 59 Left 0
SYMATTR Prefix X
SYMATTR Description Diode bridge
SYMATTR SpiceModel BRW40.asc
PIN -64 -48 NONE 0
PINATTR PinName A1
PINATTR SpiceOrder 1
PIN -64 0 NONE 0
PINATTR PinName A2
PINATTR SpiceOrder 2
PIN -64 48 NONE 0
PINATTR PinName AC2
PINATTR SpiceOrder 3
PIN 80 48 NONE 0
PINATTR PinName C2
PINATTR SpiceOrder 4
PIN 80 0 NONE 0
PINATTR PinName C1
PINATTR SpiceOrder 5
PIN 80 -48 NONE 0
PINATTR PinName AC1
PINATTR SpiceOrder 6
==============diode bridge model================
Version 4
SHEET 1 1504 692
WIRE 256 256 240 256
WIRE 272 384 240 384
WIRE 240 320 240 384
WIRE 240 384 176 384
WIRE 256 256 256 320
WIRE 256 256 336 256
WIRE 256 320 272 320
WIRE 176 256 160 256
WIRE 176 320 160 320
WIRE 336 320 352 320
WIRE 336 384 352 384
FLAG 176 384 AC2
IOPIN 176 384 In
FLAG 336 256 AC1
IOPIN 336 256 In
FLAG 160 256 A1
IOPIN 160 256 Out
FLAG 160 320 A2
IOPIN 160 320 Out
FLAG 352 320 C1
IOPIN 352 320 Out
FLAG 352 384 C2
IOPIN 352 384 Out
SYMBOL diode 272 336 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 Invisible 0
SYMATTR InstName Dc1
SYMATTR Value DBRW
SYMBOL diode 272 400 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 Invisible 0
SYMATTR InstName Dc2
SYMATTR Value DBRW
SYMBOL diode 176 336 R270
WINDOW 0 -30 28 VTop 0
WINDOW 3 0 32 Invisible 0
SYMATTR InstName Da2
SYMATTR Value DBRW
SYMBOL diode 176 272 R270
WINDOW 0 -31 29 VTop 0
WINDOW 3 -124 4 VRight 0
SYMATTR InstName Da1
SYMATTR Value BRW40
TEXT 168 488 Left 0 !.model BAS40BRW D(Ron=0.1 Roff=2meg Vfwd=0.6 Vrev=40
Rrev=0.1 mfg="Diodes Inc"); pn="BAS40BRW")
RECTANGLE Normal 344 406 169 233
Similarly for BRW70, which references a 70V (Vrev=70) BAS70BRW part.
**attempt to use SpiceLine2 attribute with leading "\n.lib "**
==============optoisolator w. shunt reference symbol=============
Version 4
SymbolType CELL
LINE Normal 96 -64 56 -64
LINE Normal 56 -48 56 -64
LINE Normal 56 -24 56 0
LINE Normal 96 0 56 0
LINE Normal 72 -48 40 -48
LINE Normal 56 -24 40 -48
LINE Normal 56 -24 72 -48
LINE Normal 72 -24 40 -24
LINE Normal -96 -48 -68 -48
LINE Normal -96 16 -72 16
LINE Normal -40 -16 -68 -48
LINE Normal -40 -16 -60 4
LINE Normal -40 -32 -40 0
LINE Normal -72 16 -56 8
LINE Normal -72 16 -64 0
LINE Normal -56 8 -64 0
LINE Normal -24 -32 -12 -36
LINE Normal -24 -32 -20 -44
LINE Normal -20 -36 -24 -32
LINE Normal 72 20 72 28
LINE Normal 72 20 40 20
LINE Normal 40 20 40 12
LINE Normal 72 44 40 44
LINE Normal 40 44 56 20
LINE Normal 72 44 56 20
LINE Normal 56 64 56 44
LINE Normal 56 20 56 0
LINE Normal 96 64 56 64
LINE Normal 64 32 96 32
RECTANGLE Normal 96 -80 -96 80
ARC Normal 4 -20 -20 -44 4 -32 -16 -36
ARC Normal 28 -20 4 -44 4 -32 28 -28
WINDOW 0 0 -64 Center 0
WINDOW 3 -31 64 Center 0
SYMATTR Value FOD2741
SYMATTR Prefix X
SYMATTR Description Shunt reference and optoisolator, transistor output
PIN 96 -64 NONE 0
PINATTR PinName LED
PINATTR SpiceOrder 1
PIN 96 0 NONE 0
PINATTR PinName COMP
PINATTR SpiceOrder 2
PIN 96 32 NONE 0
PINATTR PinName FB
PINATTR SpiceOrder 3
PIN 96 64 NONE 0
PINATTR PinName GND
PINATTR SpiceOrder 4
PIN -96 16 NONE 0
PINATTR PinName E
PINATTR SpiceOrder 5
PIN -96 -48 NONE 0
PINATTR PinName C
PINATTR SpiceOrder 6
==============optoisolator w. shunt reference model=============
Version 4
SHEET 1 1024 740
WIRE 288 416 288 464
WIRE 224 400 224 464
WIRE 384 400 384 464
WIRE 208 144 528 144
WIRE 208 240 224 240
WIRE 16 144 0 144
WIRE 16 208 0 208
WIRE 224 320 224 240
WIRE 224 240 528 240
WIRE 368 320 384 320
WIRE 288 320 288 352
WIRE 432 336 480 336
WIRE 224 464 288 464
WIRE 288 464 384 464
WIRE 384 464 432 464
WIRE 432 464 480 464
WIRE 432 384 432 464
WIRE 480 464 528 464
WIRE 480 384 480 336
WIRE 480 336 528 336
FLAG 0 144 c
IOPIN 0 144 In
FLAG 0 208 e
IOPIN 0 208 Out
FLAG 528 144 LED
IOPIN 528 144 In
FLAG 528 240 comp
IOPIN 528 240 BiDir
FLAG 528 336 fb
IOPIN 528 336 In
FLAG 528 464 ground
IOPIN 528 464 Out
SYMBOL %SCAD3%\lib\sym\Optos\CNY17-3 112 208 M0
SYMATTR InstName U1
SYMBOL %SCAD3%\lib\sym\e 384 304 M0
WINDOW 0 -14 57 Left 0
WINDOW 3 -72 58 Invisible 0
SYMATTR InstName E1
SYMATTR Value 1.0
SYMBOL %SCAD3%\lib\sym\current 480 384 R0
WINDOW 0 -22 35 Left 0
WINDOW 3 32 20 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 33 43 Left 0
SYMATTR InstName I1
SYMATTR Value 5.2
SYMATTR SpiceLine load
SYMBOL %SCAD3%\lib\sym\f 224 320 R0
WINDOW 0 -28 36 Left 0
WINDOW 3 3 35 Left 0
SYMATTR InstName F1
SYMATTR Value E1
SYMATTR Value2 -1.0
SYMBOL %SCAD3%\lib\sym\zener 304 416 R180
WINDOW 0 -35 32 Left 0
WINDOW 3 -55 3 Left 0
SYMATTR InstName D1
SYMATTR Value Z2.5V
SYMBOL %SCAD3%\lib\sym\res 384 304 R90
WINDOW 0 0 83 VBottom 0
WINDOW 3 -28 45 VTop 0
SYMATTR InstName R1
SYMATTR Value 10
TEXT -40 552 Left 0 !.model Z2.5V D(Ron=0.1 Roff=2meg Vfwd=2.5 Vrev=0.35
Rrev=0.1)\n.lib CNY17.sub
TEXT 96 336 Left 0 ;current\nmirror
TEXT 400 280 Left 0 ;voltage\nmirror
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Re: Need a model for a gas discharge tube (spark gap) and general help.
On Thu, 13 Feb 2003 20:55:11 -0000, bunnyblues2001@... wrote: I need a model for a gas discharge tube similar to the Siemens A81-
C90X, if anyone can help I'd appreciate it. I have just started to
use LTSpice and would like to know if there is any information out
there that shows how to convert a manufactures model to something
that will keep LTSpice happy. I was hoping to use the DIAC that comes
with LTSpice but found out I have to supply my own model. Any hints
for a day-old user how to do this? So far it's a cool program. Spectrum Software (makers of MicroCap) has an application note concerning gas tubes at While the syntax might be different from LTSpice, the schematics should get you started. ----- Pat Lawler <pat.lawler@...>
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Re: "Timestep too small" error while simulation
--- In LTspice@..., "analogueman2002 <rd.weaver@n...>" <rd.weaver@n...> wrote: --- In LTspice@..., "Helmut Sennewald
<helmutsennewald@y...>" <helmutsennewald@y...> wrote:
--- In LTspice@..., Panama Mike <panamatex@y...> wrote: Mike, could you tell us what tolerance is used in what type of
simulation?
I assume an .AC run doesn't use all of the tolerance settings
used in .TRAN simulation. I would try the settings below.
I am shure not all changes are useful.
Please give us a recommendation Mike.
Hello Gents,
Perhaps I can help here. Fixing convergence problems can be a
complex business but here is a sequence of things to try which has been found useful by many Spice users. It applies to .TRAN convergence problems which occur some way into the simulation rather than at the beginning.
........
Hello Russell and Mike, thanks for your advices to solve convergence problems. I will keep your messages in my archive, because I am shure that every SPICE user will run into these problems from time to time. I recommend to spend a chapter about this in the help pages of LTSpice. Best Regards Helmut
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Re: "Timestep too small" error while simulation
Helmut, Mike, could you tell us what tolerance is used in
what type of simulation? I assume an .AC run
doesn't use all of the tolerance settings used in
.TRAN simulation. I would try the settings below.
I am shure not all changes are useful. Please
give us a recommendation Mike. The tolerances that are typically most useful to loosen are abstol, vntol, and chgtol. If you loosen reltol, it's best not to loosed it too much. The "No Bypass" check box is also often an important nerve to try, especially if there are bipolar transistors in the circuit. Which tolerances are used by which analysis types: .op .dc .tran .ac .noise abstol yes yes yes no no vntol yes yes yes no no chgtol no no yes no no reltol yes yes yes no no trtol no no yes no no sstol no no no no no Note that .ac does not use any tolerances. It just does linear(complex) math as accurate as double precision allows. However, it's doing this on a linearized version of the circuit from a .op and the tolerances are used to find that solution for non-linear circuits. Sstol is steady state tolerance and is only used to set how critical the steady state detector should be. Usually this means how close the error amp current must be to zero before be considered close enough to zero. It's only used when the keyword "steady" is on the .tran command and has no impact on the accuracy of the simulation. Trtol is sort of interesting because it does not impact directly any accuracy but modifies the strategy of the .tran integrator. This is typically set to 7(it has no units) in other SPICE's. I set it to 1 in LTspice because all those SMPS macro models run better that way -- with no apparent simulation artifacts for novice users. If you do transistor level simulations, then it's probably better to loosen trtol some. --Mike __________________________________________________ Do you Yahoo!? Yahoo! Shopping - Send Flowers for Valentine's Day
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Reiner,
Analysis: Timestep too small; time=0.000173642, timestep=1.25e-019:
trouble with node "n001"
I got the same or similar error message, when I tried to simulate a square-root circuit model. Of course, it is a big different between applications, but maybe good to know, why happened it. The reason was the negative value "under" sqrt, what is imaginary number. :) . Peter
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Re: Trying to use SIDAC library
--- In LTspice@..., "Helmut Sennewald <helmutsennewald@y...>" <helmutsennewald@y...> wrote: --- In LTspice@..., "Helmut Sennewald
<helmutsennewald@y...>" <helmutsennewald@y...> wrote:
--- In LTspice@..., "bunnyblues2001
<bunnyblues2001@y...>" <bunnyblues2001@y...> wrote:
I have no experience with Spice and what I know comes from the help
file and the previous posts. I guess we all have to start
somewhere.
What I wanted to do was call up a model from a sidac library
downloaded from Intusoft. With no better ideas on how to go
about this I used the DIAC symbol from the LT library, renamed it and saved
Hello Bunny,
.....
When I run the circuit I get an
error message `Multiple instances of "any". So is there `any'
hope for me? No, the circuit is ok and will run perfectly after I really
Hello Bunny,
my last sentence could be misleading . "No" refers to "Is the
circuit ok ...". There is always hope!
Best Regards,
Helmut Helmut, why are you so smart? Worked great thanks.
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Re: "Timestep too small" error while simulation
--- In LTspice@..., "Helmut Sennewald <helmutsennewald@y...>" <helmutsennewald@y...> wrote: --- In LTspice@..., Panama Mike <panamatex@y...> wrote:
Rainer,
I'm using scad3 for a few weeks and I'm very happy
about the power and speed of simulation. Now, I
tried a more complex simualtion with
a LT1533 (I modified the sample) and got the
following error:
Analysis: Timestep too small; time=0.000173642,
timestep=1.25e-019:
trouble with node "n001"
What does that mean and how can I prevent this
error. It means the solver failed to converge for the
circuit. Usually you have to change some aspect
of the circuit to get it to run right. The
1533 is pretty complicated since it controls
the slew rate of switching via local feedback
loops. If you can't get it to run, you can
e-mail the circuit to the address on the
help=>about box for help with it. Note today
is a holiday in the USA.
Hello Mike,
Rainer could reduce the tolerances for the simulator in the Control
Panel -> SPICE box by a factor of 10 to 100.
Mike, could you tell us what tolerance is used in what type of
simulation?
I assume an .AC run doesn't use all of the tolerance settings used
in .TRAN simulation. I would try the settings below.
I am shure not all changes are useful.
Please give us a recommendation Mike.
Example:
--------
Abstol 1e-12 -> 1e-10
Reltol 1e-3 -> 1e-2
Chgtol 1e-14 -> 1e-12
TRtol 1
Voltol 1e-6 -> 1e-4
SStol 1e-3 -> 1e-2
Best Regards
Helmut Hello Gents, Perhaps I can help here. Fixing convergence problems can be a complex business but here is a sequence of things to try which has been found useful by many Spice users. It applies to .TRAN convergence problems which occur some way into the simulation rather than at the beginning. The list is in order of usefulness and should be tried in this order. 1) Check your circuit! Correct any drafting errors and be sure that there are no design errors. 2) Set RELTOL to .01 in the SPICE tab of the Control Panel (default = .001).This trades off a little precision but speeds up the simulation. 3) Set .OPTIONS ITL4=100 (default=10) This increases the number of iterations at each time step before SPICE gives up. 4) Set ABSTOL to 1E-9 (default 1E-12) and VNTOL to 1E-3 (default 1E- 9). Both of these parameters are on the SPICE tab of the Control Panel. They reduce the required precision slightly to make the transient solution easier to find. The default values are intended for use with IC designs. The vales suggested here are more appropriate for power supply circuits. 5) Add realistic parasitics to your circuit. e.g. 3pF across diodes and 5pF across BJT's. Add 100MEG to 1G resistors from each node to ground. (Unfortunately LTSpice does not appear to have the RSHUNT .OPTIONS parameter which would do this automatically). 6) Change the integration method to Gear (default is modified trap). This parameter is also found on the SPICE tab of the Control Panel. It should be used in conjunction with RELTOL = .01. Gear integration tends to produce more stable if slightly less precise results than trapezoidal integration. It is the preferred method for simulating power circuitry as it performs better in situations where there is ringing. I hope this helps. Russell
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Re: "Timestep too small" error while simulation
--- In LTspice@..., Panama Mike <panamatex@y...> wrote: Rainer,
I'm using scad3 for a few weeks and I'm very happy
about the power and speed of simulation. Now, I
tried a more complex simualtion with
a LT1533 (I modified the sample) and got the
following error:
Analysis: Timestep too small; time=0.000173642,
timestep=1.25e-019:
trouble with node "n001"
What does that mean and how can I prevent this
error. It means the solver failed to converge for the
circuit. Usually you have to change some aspect
of the circuit to get it to run right. The
1533 is pretty complicated since it controls
the slew rate of switching via local feedback
loops. If you can't get it to run, you can
e-mail the circuit to the address on the
help=>about box for help with it. Note today
is a holiday in the USA.
Hello Mike, Rainer could reduce the tolerances for the simulator in the Control Panel -> SPICE box by a factor of 10 to 100. Mike, could you tell us what tolerance is used in what type of simulation? I assume an .AC run doesn't use all of the tolerance settings used in .TRAN simulation. I would try the settings below. I am shure not all changes are useful. Please give us a recommendation Mike. Example: -------- Abstol 1e-12 -> 1e-10 Reltol 1e-3 -> 1e-2 Chgtol 1e-14 -> 1e-12 TRtol 1 Voltol 1e-6 -> 1e-4 SStol 1e-3 -> 1e-2 Best Regards Helmut
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Re: Trying to use SIDAC library
--- In LTspice@..., "Helmut Sennewald <helmutsennewald@y...>" <helmutsennewald@y...> wrote: --- In LTspice@..., "bunnyblues2001
<bunnyblues2001@y...>" <bunnyblues2001@y...> wrote:
I have no experience with Spice and what I know comes from the help file and the previous posts. I guess we all have to start
somewhere.
What I wanted to do was call up a model from a sidac library
downloaded from Intusoft. With no better ideas on how to go about
this I used the DIAC symbol from the LT library, renamed it and
saved
Hello Bunny,
.....
When I run the circuit I get an
error message `Multiple instances of "any". So is there `any'
hope for me? No, the circuit is ok and will run perfectly after I really
Hello Bunny, my last sentence could be misleading . "No" refers to "Is the circuit ok ...". There is always hope! Best Regards, Helmut
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Re: Trying to use SIDAC library
--- In LTspice@..., "bunnyblues2001 <bunnyblues2001@y...>" <bunnyblues2001@y...> wrote: I have no experience with Spice and what I know comes from the help
file and the previous posts. I guess we all have to start somewhere.
What I wanted to do was call up a model from a sidac library
downloaded from Intusoft. With no better ideas on how to go about
this I used the DIAC symbol from the LT library, renamed it and saved Hello Bunny, I downloaded this library directly from Teccor. Click on "SIDAC" and download the library. It contains the library file "SIDAC:LIB" where you will find amomg others the "K1100E70". Please use this original library. Either you rename it to then to DEMSIDAC.LIB or you have to change the name in your ".include" statement to ".include SIDAC.LIB" . it to the symbol folder. I dropped it on my schematic and opened up
the Component Attribute Editor. It's ok, but you could also move your cursor over the text DIAC and right-click your mouse. Replace the word DIAC with K1100E70. (K1100E70 is the model in the library). On the schematic I dropped
a Spice directive .inc demsidac.lib. Still all perfect. But it was not done in your attached file. It still has the value "DIAC" there. When I run the circuit I get an
error message `Multiple instances of "any". So is there `any' hope
for me? No, the circuit is ok and will run perfectly after I really changed "DIAC" to "K1100E70". I have attached the corrected file and again, please download the SIDAC library from the above mentioned original source. Best Regards, Helmut Version 4 SHEET 1 892 692 WIRE -64 272 64 272 WIRE -96 272 -64 272 WIRE -64 336 -64 352 WIRE -64 352 64 352 WIRE -720 352 -720 368 WIRE -64 352 -304 352 WIRE -720 272 -304 272 WIRE -304 272 -176 272 WIRE -304 336 -304 352 WIRE -304 352 -720 352 FLAG -720 368 0 SYMBOL C:\Program\Files\LTC\SwCADIII\lib\sym\voltage -720 256 R0 WINDOW 3 24 104 Invisible 0 WINDOW 123 0 0 Left 0 WINDOW 39 24 132 Left 0 SYMATTR Value EXP(0 1000 0 1.2us 10us 50us) SYMATTR SpiceLine Rser=.1 Cpar=.01uf SYMATTR InstName V1 SYMBOL C:\Program\Files\LTC\SwCADIII\lib\sym\ind -192 288 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L3 SYMATTR Value 10? SYMBOL C:\Program\Files\LTC\SwCADIII\lib\sym\res 48 256 R0 SYMATTR InstName R1 SYMATTR Value 1 SYMBOL C:\Program\Files\LTC\SwCADIII\lib\sym\polcap -80 272 R0 WINDOW 3 24 64 Left 0 SYMATTR Value 1.4? SYMATTR InstName C2 SYMATTR Description Capacitor SYMATTR Type cap SYMBOL C:\Program\Files\LTC\SwCADIII\lib\sym\Misc\DIAC -336 272 R0 SYMATTR InstName U1 SYMATTR Value K1100E70 TEXT -754 408 Left 0 !.tran 0 .001s 1us 1us TEXT -480 464 Left 0 !.include demsidac.lib
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Re: "Timestep too small" error while simulation
Mike,
thanks, for the quick answer!
I played a little around and I was able to complete simulate the
circuit. The wave-results are not as I wanted and I think I need a lot
more simulations until my circuit will work.
PM> can only stipulate a smaller one. You might
PM> try the keyword "startup" on the .tran
PM> command since it looks like your having
PM> trouble with the intial conditions of your
PM> simulation.
When I got another timestep error, LTspice ran a few time (3ms of
desired 10ms), until the error occurs. Are the data "in front of" the
error correct? Am I near some limits of the simulator, that causes the
problems of convergence? Are there some serial/parallel R/C/L I need
to take care about? Can I trust it?
Sorry for that elementary questions. I thought simulating a circuit is
easier... :-)
Gru, Rainer
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Trying to use SIDAC library
I have no experience with Spice and what I know comes from the help
file and the previous posts. I guess we all have to start somewhere.
What I wanted to do was call up a model from a sidac library
downloaded from Intusoft. With no better ideas on how to go about
this I used the DIAC symbol from the LT library, renamed it and saved
it to the symbol folder. I dropped it on my schematic and opened up
the Component Attribute Editor. In the value field I typed K1100E70
(K1100E70 is the model in the library). On the schematic I dropped a
Spice directive .inc demsidac.lib. When I run the circuit I get an
error message `Multiple instances of "any". So is there `any' hope
for me?
Version 4
SHEET 1 892 692
WIRE -64 272 64 272
WIRE -96 272 -64 272
WIRE -64 336 -64 352
WIRE -64 352 64 352
WIRE -720 352 -720 368
WIRE -64 352 -304 352
WIRE -720 272 -304 272
WIRE -304 272 -176 272
WIRE -304 336 -304 352
WIRE -304 352 -720 352
FLAG -720 368 0
SYMBOL C:\Program\ Files\LTC\SwCADIII\lib\sym\voltage -720 256 R0
WINDOW 3 24 104 Invisible 0
WINDOW 123 0 0 Left 0
WINDOW 39 24 132 Left 0
SYMATTR Value EXP(0 1000 0 1.2us 10us 50us)
SYMATTR SpiceLine Rser=.1 Cpar=.01uf
SYMATTR InstName V1
SYMBOL C:\Program\ Files\LTC\SwCADIII\lib\sym\ind -192 288 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 5 56 VBottom 0
SYMATTR InstName L3
SYMATTR Value 10?
SYMATTR SpiceLine Ipk=3.9 Rser=0.038 Rpar=94000 Cpar=2.8p
mfg="Coilcraft" pn="DO3316P-103"
SYMBOL C:\Program\ Files\LTC\SwCADIII\lib\sym\res 48 256 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL C:\Program\ Files\LTC\SwCADIII\lib\sym\polcap -80 272 R0
WINDOW 3 24 64 Left 0
SYMATTR Value 1.4?
SYMATTR InstName C2
SYMATTR Description Capacitor
SYMATTR Type cap
SYMATTR SpiceLine V=50 Irms=2 Rser=.007 MTBF=0 Lser=0 ppPkg=0
SYMBOL C:\Program\ Files\LTC\SwCADIII\lib\sym\Misc\DIAC1 -336 272 R0
SYMATTR InstName U1
TEXT -754 408 Left 0 !.tran 0 .001s 1us 1us
TEXT -480 464 Left 0 !.include demsidac.lib
* C:\Program Files\LTC\SwCADIII\My circuits\filter.asc
V1 N002 0 EXP(0 1000 0 1.2us 10us 50us) Rser=.1 Cpar=.01uf
L3 N002 N001 10? Ipk=3.9 Rser=0.038 Rpar=94000 Cpar=2.8p
mfg="Coilcraft" pn="DO3316P-103"
R1 N001 0 1
C2 N001 0 1.4? V=50 Irms=2 Rser=.007 MTBF=0 Lser=0 ppPkg=0
XU1 N002 0 K1100E70
.tran 0 .001s 1us 1us
.include demsidac.lib
.backanno
.end
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Mike Engelhardt