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Apologies. It's a bad habit of mine not read instructions before acting. What should I do now? About My Project I am not really familiar with HSPICE and the model file is designed for that APP. And I

But you did not read and follow what John Woodgate wrote!? Neither did you follow the instructions on the group's main webpage! Shame on you for not even trying. Andy

There is a special very hot place reserved for supervisors who set students problems that the supervisor doesn't know how to solve. You might do better to use LTspice, but work only with the .ASC and

OK, here is the dumbed-down version of what I wrote: Your model files ("PTM" files) *will not work in LTspice*. Don't try.? Get the right model files for 20 nm and for the SPICE simulator you intend

I have uploaded the file also i have notified you guys.

I am just a student and half of the things you said went bouncer T-T. My HoD told me to make this project because i attended Semi-conductor training program in SVNIT SURAT. Even he don't know how to

Note that simply scaling the dimensions as you did, does not get you from a 180 nm process to a 20 nm process. There are significant changes necessary in the model (PTM) files themselves.? You should

Did you read the advice already given? Did you read the guidelines for this group ( /g/LTspice ) where you asked the question? Please go back to the starting gate and begin again.?

LTspice does not support "LEVEL=72" MOSFET models.? If those are the only models you have for your 20 nm devices, then you will need to use another SPICE program with it.? Probably that is HSPICE.

Read the message! *BOLD TYPE*

How should I upload ? [email protected]> wrote:

We can't help much unless you let us see more of what you are doing. Upload your .ASC file AND all the other files required to run the simulation, but not .RAW? and .LOG files or pictures,? in a ZIP

I am trying to build 6T SRAM using 20nm but when i run the simulation i am having the errors saying parameter level = 72 and also other bunch of errors. my 180nm file ran properly but when i tried for

On 03/04/2025 10:34, Tony Casey wrote: > On 03/04/2025 09:26, jacfev via groups.io wrote: >> My question is multiple: >> 1. What are the influential spice parameters that optimize the switching speed?

I agree with Tony. If Bf is found to affect switching speed, we need to see the test circuit .ASC that you are using, because it's probably not the optimum.

On 03/04/2025 09:55, eewiz via groups.io wrote: > Gentlemen, those CD4x and 74HC libraries have two required values that appear on a symbol's SpiceModel line. > ctrl-right-click a logic symbol to

This is not such a simple question. What are your parameters for switching speed? Presumably rise and fall times? How about delays times? You can still have fast rise and fall times, but with a

Gentlemen, those CD4x and 74HC libraries have two required values that appear on a symbol's SpiceModel line. ctrl-right-click a logic symbol to alter its SpiceModel line. By default the two values are

Hello, My question is multiple: 1. What are the influential spice parameters that optimize the switching speed? To my knowledge, it's mainly Bf that seems to be the most important for increasing the

Those messages are not significant LTspice error messages. They are probably due to over-keen syntax checks that were introduced in some 24.1.x versions of LTspice. I don't see them in my .LOG file,