--- In LTspice@..., "ranga_rajanus" <ranga_rajan@e...>
wrote:

Hello all,

Let me first thank Linear for such a nice spice simulator
that too free! I am relatively new to this field and have a
requirement to simulate a circuit based on INA 103 IN AMP from TI.

I

have gone through all the messages /suggestions about how to use a
non vendor provided spice modles but some how not been able to make
use of them for my need as some error or other keeps coming up when

i

simulate non LT components.

My version of LT SWCADIII is now 2.03f and this has a symbol
editor and one can change the order the pins ie spice order to be
considered by the simulator. In effect the references of using BURR

n

BROWN models in messages is no longer valid.
Would some one please write a clear note on how to use vendor
suppled spice modles for use in LT spice. It would be very helpful
also if a short primer as to whats *.MOD file, Whats *.CIR files

and

how a custom *.LIB file can be made ete.. are answered and may be

LT

may consider adding this to help file of LT spice. WHen i did a cut
and paste of a model in to LTC.LIB file there were many errors
reported. MAy be i did something wrong!

The chips i am interested in are INA 103, OPA 4277,OPA 2604
all and AD 625,AD 210. Would some one be kind enough to model at
least INA 103 and give the procedure.

Hello Ranga,
I am shure that I have explained it more than once in this group how
to add a new subcircuit model and all these "old" instructions are
still valid.

Just make a copy of the LT1013.asy -> OPA2604.asy . Open this new
file with a text editor. Replace all the obvious text LT1013 with
OPA2604. Replace the word ltc.lib with the name of your model file
ore the name of a library file which includes your model. Then ompare
the pin order of your symbol with the pin order of your model file.
You have to change it in the symbol if it doesn't match the order in
the model file. Now save the new symbol file. By the way, it seems no
longer necessary to restart LTSPICE after that action.

Some hints about file organization.
If you reference the SpiceModel with a file name without path, then
this model file has to be either in the LTSPICE "Lib" durectory or in
the working directory of your schematic file.
I recommend to make a folder "Private" below this "Lib" directory.
THen your reference name of the SpiceModel in the symbol file has to
be "Private&#92;name.xyz". You can put as many models you want into one
file if this file name ends with .lib .
The same procedure can be applied to the OPA4277(=OPA277).
Don't waste any time trying to build a quad model with 4 equal opamps.

The INA103 model file is lacking some features of the real part,
because the provided model has at least 6 pins too less. I had to
sketch the top level of the circuit from the netlist to see where are
the missing pins. Then I extended the model according to the
datasheet with these pins.


My files for the Ina103 are in the Files-folders of this group.
(ina103.sym, ina103.sub, ina103_test.asc).
I have also solved a convergence problem in the .OP analysis with the
additonal command line .OPTIONS Gmin=1e-11.

Besr Regards
Helmut

PS: This was a (too)very time consuming task for me. I hope you can
solve the other models yourself.

My changes:

* CONNECTIONS: NON-INVERTING INPUT
* | INVERTING INPUT
* | | POSITIVE POWER SUPPLY
* | | | NEGATIVE POWER SUPPLY
* | | | | OUTPUT
* | | | | | REFERENCE
* | | | | | | GAIN SENSE 1
* | | | | | | | GAIN SENSE 2
* | | | | | | | |
*.SUBCKT INA103 1 2 3 4 5 8 9 10
*** -RG +RG -GD +GD SNS G100
.SUBCKT INA103 1 2 3 4 5 8 9 10 109 110 11 12 105 111

*** Change, add resistor for gain = 100, HS 6/8/2003
R910 109 111 60.6

*** Change, seperate connection SENSE, HS 6/8/2003
*R2 13 5 5.9994K
R2 13 105 5.9994K

*** Change, seperate connection -Rg, HS 6/8/2003
*R1FB 9 11 3.0000K
R1FB 109 11 3.0000K

*** Change, seperate connection +Rg, HS 6/8/2003
*R2FB 10 12 3.0000K
R2FB 110 12 3.0000K

Hi all,

I'm trying to simulate a very simple 3 stage differential amplifier
in LTSpice. The design works well in Hspice. However, when I try to
run it under LTSpice, I got the following output in the Spice error
log:

Starting Gmin stepping
Gmin = 10
Gmin = 1.07374
Gmin = 0.115292
Gmin = 0.0123794
Gmin = 0.00132923
Gmin = 0.000142725
vernier = 0.5
vernier = 0.25
vernier = 0.125
vernier = 0.0625
vernier = 0.03125
vernier = 0.015625
vernier = 0.0078125
Gmin = 9.13439e-005
vernier = 0.00390625
vernier = 0.00195313
vernier = 0.000976563
vernier = 0.000488281
vernier = 0.000244141
vernier = 0.00012207
vernier = 6.10352e-005
vernier = 3.05176e-005
vernier = 1.52588e-005
vernier = 7.62939e-006
Gmin = 9.13439e-005
vernier = 3.8147e-006
vernier = 1.90735e-006
vernier = 9.53674e-007
vernier = 4.76837e-007
vernier = 2.38419e-007
vernier = 1.19209e-007
vernier = 5.96046e-008
vernier = 2.98023e-008
vernier = 1.49012e-008
vernier = 7.45058e-009
Gmin = 9.13439e-005
vernier = 3.72529e-009
vernier = 1.86265e-009
vernier = 9.31323e-010
vernier = 4.65661e-010
vernier = 2.32831e-010
vernier = 1.16415e-010
vernier = 5.82077e-011
vernier = 2.91038e-011
vernier = 1.45519e-011
vernier = 7.27596e-012
Gmin = 9.13439e-005
vernier = 3.63798e-012
vernier = 1.81899e-012
vernier = 9.09495e-013
vernier = 4.54747e-013
vernier = 2.27374e-013
vernier = 1.13687e-013
vernier = 5.68434e-014
vernier = 2.84217e-014
vernier = 1.42109e-014
vernier = 7.10543e-015
Gmin = 9.13439e-005
vernier = 5.32907e-015
Gmin = 0
Gmin stepping failed

Starting source stepping
Source Step = 3.0303%
Source Step = 3.03031%
vernier = 9.53674e-007
Source Step = 3.0303%
vernier = 9.09495e-013
Source stepping failed

Fatal Error: doAnalyses: Iteration limit reached


Here is my opamp definition:

* |--Non-Inverting Input
* | |--Inverting Input
* | | |--Output
* | | | |--positive supply
* | | | | |--negative supply
.subckt opamp in_pos in_neg out vdd gnd
* The current mirror
Rref bias0 gnd 40.2k
x0 ss bias0 vdd vdd p1_5 w=200u
x13 bias0 bias0 vdd vdd p1_5 w=200u
* The diff pair
x1 load1 in_neg ss ss p1_5 w=200u
x2 load2 in_pos ss ss p1_5 w=200u
* The load
x7 load1 load1 gnd gnd n2_0 w=50u
x8 load2 load1 gnd gnd n2_0 w=50u
* The second stage
x11 out bias0 vdd vdd p1_5 w=400u
x12 out load2 gnd gnd n1_5 w=130u
* Compensation
rcoup load2 int0 1k
ccoup int0 out 3p
.ends opamp


And this is my model definition:

*** Stack of 3, nmos
.subckt n1_5 drain gate source sub w=15u
M2a drain gate srca sub nmos W='w' L='0.5u'
+AD='1.5u*w' PD='2*(1.5u+w)' AS='1.5u*w' PS='2*(1.5u+w)'
M2b srca gate srcb sub nmos W='w' L='0.5u'
+AD=0 PD=0 AS='1.5u*w' PS='2*(1.5u+w)'
M2c srcb gate source sub nmos W='w' L='0.5u'
+AD=0 PD=0 AS='1.5u*w' PS='2*(1.5u+w)'
.ends n1_5

*Stack of 3, pmos
.subckt p1_5 drain gate source well w=15u
M2a drain gate srca well pmos W='w' L='0.5u'
+AD='1.5u*w' PD='2*(1.5u+w)' AS='1.5u*w' PS='2*(1.5u+w)'
M2b srca gate srcb well pmos W='w' L='0.5u'
+AD=0 PD=0 AS='1.5u*w' PS='2*(1.5u+w)'
M2c srcb gate source well pmos W='w' L='0.5u'
+AD=0 PD=0 AS='1.5u*w' PS='2*(1.5u+w)'
.ends p1_5

* Stack of 4, nmos
.subckt n2_0 drain gate source sub w=15u
M2a drain gate srca sub nmos W='w' L='0.5u'
+AD='1.5u*w' PD='2*(1.5u+w)' AS='1.5u*w' PS='2*(1.5u+w)'
M2b srca gate srcb sub nmos W='w' L='0.5u'
+AD=0 PD=0 AS='1.5u*w' PS='2*(1.5u+w)'
M2c srcb gate srcc sub nmos W='w' L='0.5u'
+AD=0 PD=0 AS='1.5u*w' PS='2*(1.5u+w)'
M2d srcc gate source sub nmos W='w' L='0.5u'
+AD=0 PD=0 AS='1.5u*w' PS='2*(1.5u+w)'
.ends n2_0

* Level 3 BSIM MOSFET Models
.MODEL NMOS NMOS LEVEL=3 PHI=0.7 TOX=9.5E-09 XJ=0.2U TPG=1
+ VTO=0.7 DELTA=8.8E-01 LD=5E-08 KP=1.56E-04
+ UO=420 THETA=2.3E-01 RSH=2.0E+00 GAMMA=0.62
+ NSUB=1.40E+17 NFS=7.20E+11 VMAX=1.8E+05 ETA=2.125E-02
+ KAPPA=1E-01 CGDO=3.0E-10 CGSO=3.0E-10
+ CGBO=4.5E-10 CJ=5.50E-04 MJ=0.6 CJSW=3E-10
+ MJSW=0.35 PB=1.1


I have a strong suspicion that LTSpice doesn't like my model
definitios. But given the scarce error messages, I'm unable to trace
down any further. I would greatly appreciate anyone who can help me.

Thanks,

Hao

Hello all,

Let me first thank Linear for such a nice spice simulator
that too free! I am relatively new to this field and have a
requirement to simulate a circuit based on INA 103 IN AMP from TI. I
have gone through all the messages /suggestions about how to use a
non vendor provided spice modles but some how not been able to make
use of them for my need as some error or other keeps coming up when i
simulate non LT components.

My version of LT SWCADIII is now 2.03f and this has a symbol
editor and one can change the order the pins ie spice order to be
considered by the simulator. In effect the references of using BURR n
BROWN models in messages is no longer valid.
Would some one please write a clear note on how to use vendor
suppled spice modles for use in LT spice. It would be very helpful
also if a short primer as to whats *.MOD file, Whats *.CIR files and
how a custom *.LIB file can be made ete.. are answered and may be LT
may consider adding this to help file of LT spice. WHen i did a cut
and paste of a model in to LTC.LIB file there were many errors
reported. MAy be i did something wrong!

The chips i am interested in are INA 103, OPA 4277,OPA 2604
all and AD 625,AD 210. Would some one be kind enough to model at
least INA 103 and give the procedure.

Warm regards
Ranga Rajan

Mike, could you add the ability to print the DC Operating Point
information from a .op run? I know that I can cut and paste to a
text editor, but a print command would be easier.

Thanks for the example. It looks like the problem only happens
when ploting expressions of stepped data of complex data. I'll
publish the fix in a few days.

Thanks again for the report.

--Mike

--- Brad Suppanz <suppanz@...> wrote:

Try plotting this expression with the attached file:

V(n001)/i(c1)


(image file also attached)

Brad

Panama Mike <panamatex@...> wrote:
Brad,

While using the .step command to sweep parameters, I am getting
extraneous lines in the waveform viewer that go from the end of one
trace to the beginning of another trace. This only happens when
plotting an algebraic expression such as "V(n002)/i(c1)".

Could you send me the file(s) I need to duplicate this. I'd
appreciate it.

--Mike

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ATTACHMENT part 2 application/octet-stream name=test.asc

ATTACHMENT part 3 image/pjpeg name=image002.jpg

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---

Do you Yahoo!?
Free with sync to Outlook(TM).

Brad,

While using the .step command to sweep parameters, I am getting
extraneous lines in the waveform viewer that go from the end of one
trace to the beginning of another trace. This only happens when
plotting an algebraic expression such as "V(n002)/i(c1)".

Could you send me the file(s) I need to duplicate this. I'd
appreciate it.

--Mike

__________________________________
Do you Yahoo!?
Yahoo! Calendar - Free online calendar with sync to Outlook(TM).

While using the .step command to sweep parameters, I am getting
extraneous lines in the waveform viewer that go from the end of one
trace to the beginning of another trace. This only happens when
plotting an algebraic expression such as "V(n002)/i(c1)".

Brad




---

Steve,

> The modulator block is a special function that is relatively
> undocumented. I find it quite useful as it would take many primitive
> functions to perform the same function.
>
> I have been using the modulator block to convert current to
> frequency. I do this by inserting a small series resistor (less than
> 1 ohm) into the circuit and connecting the unmarked lower terminal of
> the block to one side of the resistor and the FM terminal of the
> block to the other side of the resistor.
>
> I am assuming that the unmarked terminal is some kind of reference
> terminal for the modulator function. Of course, I'm only guessing!
> However, it seems to work quite well. I do notice, however, that when
> the current sensing resistor is connected in the higher voltage end
> of the circuit that the modulator does not work as well. In my
> application this voltage can be several kilovolts. I get the
> impression that there are some input resistances associated with
> this "reference" terminal, but again this is only a guess.
>
> Can you provide any additional information about this block such as
> an equivalent circuit or netlist of some kind, or just a description
> of what the unmarked terminal is?

The unmarked terminal is the device's ground connection.
Yes, it serves as reference for the inputs and current return
for the output.? You set the mapping between the voltage
on the FM input and instantaneous frequency by the values
of the mark and space.? See the example circuit included
as ./examples/Educational/PLL.asc and there's brief
documentation in the help section
Appendixes=>Symbols=>Special Functions=>MODULATE

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---

Do you Yahoo!?
Free with sync to Outlook(TM).

Steve,

The modulator block is a special function that is relatively
undocumented. I find it quite useful as it would take many primitive
functions to perform the same function.

I have been using the modulator block to convert current to
frequency. I do this by inserting a small series resistor (less than
1 ohm) into the circuit and connecting the unmarked lower terminal of
the block to one side of the resistor and the FM terminal of the
block to the other side of the resistor.

I am assuming that the unmarked terminal is some kind of reference
terminal for the modulator function. Of course, I'm only guessing!
However, it seems to work quite well. I do notice, however, that when
the current sensing resistor is connected in the higher voltage end
of the circuit that the modulator does not work as well. In my
application this voltage can be several kilovolts. I get the
impression that there are some input resistances associated with
this "reference" terminal, but again this is only a guess.

Can you provide any additional information about this block such as
an equivalent circuit or netlist of some kind, or just a description
of what the unmarked terminal is?

The unmarked terminal is the device's ground connection.
Yes, it serves as reference for the inputs and current return
for the output. You set the mapping between the voltage
on the FM input and instantaneous frequency by the values
of the mark and space. See the example circuit included
as ./examples/Educational/PLL.asc and there's brief
documentation in the help section
Appendixes=>Symbols=>Special Functions=>MODULATE

__________________________________
Do you Yahoo!?
Yahoo! Calendar - Free online calendar with sync to Outlook(TM).

Gentlemen -

The modulator block is a special function that is relatively
undocumented. I find it quite useful as it would take many primitive
functions to perform the same function.

I have been using the modulator block to convert current to
frequency. I do this by inserting a small series resistor (less than
1 ohm) into the circuit and connecting the unmarked lower terminal of
the block to one side of the resistor and the FM terminal of the
block to the other side of the resistor.

I am assuming that the unmarked terminal is some kind of reference
terminal for the modulator function. Of course, I'm only guessing!
However, it seems to work quite well. I do notice, however, that when
the current sensing resistor is connected in the higher voltage end
of the circuit that the modulator does not work as well. In my
application this voltage can be several kilovolts. I get the
impression that there are some input resistances associated with
this "reference" terminal, but again this is only a guess.

Can you provide any additional information about this block such as
an equivalent circuit or netlist of some kind, or just a description
of what the unmarked terminal is?

Thanking you in advance.....

Steve Steckler

开云体育

---

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Brad,

Thank you very much for sending me the schematic to my other
account.

1.) B4 and B6
I had to use two sources in series instead of just one because the
_expression would not evaluate correctly if one of the terms goes to
zero in the ac analysis. If one term goes to zero, the whole
_expression evaluates to "-1.#INFTdB" even if the other term is not
zero.

This looks like a pilot error. In the appended .asc file, node X and
node Y are two different ways of recombining the sources into one.
Node X, Y, and duty 3 are identical.

2.) B2
B2 would not evaluate correctly when using the _expression "I=i(B3)*v
(duty)". This was fixed by adding V9 to sense the current of B3 and
using the _expression "I=i(V9)*v(duty)".

You can only call currents from voltages in behavioral sources and depend
on it working. If you call a current from anything but a voltage source
it won't work in feedback loops or small signal analysis. This is sort
of explained in the help in section LTspice=>Circuit Elements=>A. Arbitrary
behavioral source

3.) Dividing by zero in .param
Dividing by zero in a .param _expression appears to be ignored and
gives the result as if dividing by one. For example:
.param Ry=Rs*Vin/Vramp
is effectively
.param Ry=Rs*Vin

Ah, yes, I'll detect this and map infinity to 1e308 and negative infinity
to -1e308. And issue a warning. Thanks for the report!

--Mike

--- .asc file ---
Version 4
SHEET 1 3060 1048
WIRE 96 80 288 80
WIRE 352 208 352 272
WIRE 352 272 560 272
WIRE 560 272 560 208
WIRE 352 128 352 80
WIRE 560 128 560 80
WIRE 560 80 608 80
WIRE 288 80 352 80
WIRE 608 80 784 80
WIRE 352 272 288 272
WIRE 560 272 1248 272
WIRE 288 272 208 272
WIRE 1440 128 1440 80
WIRE 1440 80 1504 80
WIRE 1440 208 1440 272
WIRE 1504 80 1552 80
WIRE 96 272 96 208
WIRE 96 128 96 80
WIRE 1248 80 1248 128
WIRE 1248 272 1248 208
WIRE 208 304 208 272
WIRE 208 272 96 272
WIRE -96 448 -96 400
WIRE -96 400 -48 400
WIRE -96 592 -96 528
WIRE 160 400 192 400
WIRE 1024 80 1248 80
WIRE 560 -208 560 -240
WIRE 560 -240 688 -240
WIRE 1360 -240 1360 -192
WIRE 1360 -48 1008 -48
WIRE 560 -48 560 -128
WIRE 768 -112 768 -48
WIRE 768 -48 560 -48
WIRE 768 -192 768 -240
WIRE 880 -240 1008 -240
WIRE 1296 -240 1360 -240
WIRE 688 -240 768 -240
WIRE 96 400 160 400
WIRE 880 -192 880 -240
WIRE 768 -240 880 -240
WIRE 880 -112 880 -48
WIRE 768 -48 880 -48
WIRE -48 400 16 400
WIRE 560 -48 416 -48
WIRE 416 -48 272 -48
WIRE 208 -16 208 -48
WIRE 208 -48 96 -48
WIRE 1360 -112 1360 -48
WIRE 1568 -192 1568 -240
WIRE 1568 -240 1632 -240
WIRE 1568 -112 1568 -48
WIRE 1632 -240 1760 -240
WIRE 1824 -192 1824 -240
WIRE 1824 -240 1888 -240
WIRE 1824 -112 1824 -48
WIRE 1888 -240 1936 -240
WIRE 1760 -240 1760 -48
WIRE 1760 -48 1824 -48
WIRE 1152 -240 1216 -240
WIRE 416 -128 416 -48
WIRE 416 -208 416 -240
WIRE 416 -240 368 -240
WIRE 96 -240 96 -208
WIRE 96 -128 96 -48
WIRE 272 -96 272 -48
WIRE 272 -176 272 -240
WIRE 272 -48 208 -48
WIRE 272 -240 96 -240
WIRE 368 -240 272 -240
WIRE 1008 -192 1008 -240
WIRE 1008 -240 1072 -240
WIRE 1008 -112 1008 -48
WIRE 1008 -48 880 -48
WIRE 1920 272 1920 208
WIRE 1920 128 1920 80
WIRE 1920 80 1968 80
WIRE 1968 80 2000 80
WIRE 2096 272 2096 208
WIRE 2096 128 2096 80
WIRE 2096 80 2144 80
WIRE 2144 80 2176 80
WIRE 864 80 944 80
WIRE 1568 -480 1568 -528
WIRE 1568 -400 1568 -336
WIRE 2016 -480 2016 -528
WIRE 2016 -400 2016 -336
FLAG 288 80 act
FLAG 608 80 cmn
FLAG 288 272 pas
FLAG 1440 272 0
FLAG 1504 80 duty
FLAG 208 304 0
FLAG -96 592 0
FLAG 160 400 vc
FLAG 688 -240 cmn2
FLAG -48 400 vc1
FLAG 208 -16 0
FLAG 1568 -48 0
FLAG 1632 -240 duty2
FLAG 1888 -240 duty3
FLAG 368 -240 act2
FLAG 1920 272 0
FLAG 1968 80 test1
FLAG 2096 272 0
FLAG 2144 80 test2
FLAG 1568 -336 0
FLAG 1568 -528 X
FLAG 2016 -336 0
FLAG 2016 -528 Y
SYMBOL bv 1440 112 R0
SYMATTR InstName B1
SYMATTR Value V=(v(cmn)-v(pas))/(v(act)-v(pas)+1u)
SYMBOL bi 352 128 R0
SYMATTR InstName B2
SYMATTR Value I=i(v9)*v(duty)
SYMBOL bi2 560 128 R0
SYMATTR InstName B3
SYMATTR Value I=v(vc)/Rs - (v(act)-v(pas))*v(duty)*(1-v(duty))*Ts/(2*L)
SYMBOL battery 96 112 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value {Vin}
SYMBOL battery 1248 112 R0
SYMATTR InstName V3
SYMATTR Value {Vout}
SYMBOL voltage -96 432 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V4
SYMATTR Value {Vc}
SYMBOL ind 928 96 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 5 56 VBottom 0
SYMATTR InstName L1
SYMATTR Value {L}
SYMATTR SpiceLine Rser=0
SYMBOL bi2 560 -208 R0
SYMATTR InstName B44
SYMATTR Value I=v(vc1)/Rs
SYMBOL res 752 -208 R0
SYMATTR InstName Rx
SYMATTR Value {Rx}
SYMBOL ind 1200 -224 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 5 56 VBottom 0
SYMATTR InstName L2
SYMATTR Value {L}
SYMATTR SpiceLine Rser=0
SYMBOL bv 0 400 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 -32 56 VBottom 0
SYMATTR InstName B5
SYMATTR Value V=Vramp*v(duty)
SYMBOL res 864 -208 R0
SYMATTR InstName Ry
SYMATTR Value {Ry}
SYMBOL battery 1360 -208 R0
SYMATTR InstName V5
SYMATTR Value {Vout}
SYMBOL bv 1568 -208 R0
SYMATTR InstName B4
SYMATTR Value V=v(cmn2)/Vin
SYMBOL bv 1824 -208 R0
SYMATTR InstName B6
SYMATTR Value V=-v(act2)*Vout/(Vin*Vin)
SYMBOL bi 416 -208 R0
SYMATTR InstName B7
SYMATTR Value I=i(v1)*D
SYMBOL voltage 1056 -240 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 -32 56 VBottom 0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL battery 96 -224 R0
WINDOW 123 21 130 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value {Vin}
SYMBOL bi 272 -176 R0
SYMATTR InstName B8
SYMATTR Value I=v(duty3)*Icmn2
SYMBOL bi2 1008 -192 R0
SYMATTR InstName B10
SYMATTR Value I=(gm1+gm2)*v(act2)
SYMBOL battery 1920 112 R0
SYMATTR InstName V7
SYMATTR Value {Icmn2}
SYMBOL battery 2096 112 R0
SYMATTR InstName V8
SYMATTR Value {Ry}
SYMBOL voltage 768 80 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 -32 56 VBottom 0
SYMATTR InstName V9
SYMATTR Value 0
SYMBOL bv 1568 -496 R0
SYMATTR InstName B9
SYMATTR Value V=v(cmn2)/Vin-v(act2)*Vout/(Vin*Vin)
SYMBOL bv 2016 -496 R0
SYMATTR InstName B11
SYMATTR Value V=(v(cmn)-v(pas))/(v(act)-v(pas))
TEXT 856 408 Left 0 !.param Rs=0.1 L=1.5u Ts=5u
TEXT 358 388 Left 0 !;tran 1m uic
TEXT 360 416 Left 0 !;op
TEXT 536 384 Left 0 !.nodeset v(cmn)=2.5
TEXT 536 408 Left 0 !.ac dec 25 1 10meg
TEXT -136 -232 Left 0 ;Small-Signal Model
TEXT -136 88 Left 0 ;Nonlinear&#92;nAveraged Model
TEXT 856 384 Left 0 !.param Vin=10 Vout=2.5 Vramp=1u D=Vout/Vin
TEXT 856 432 Left 0 !.param Vc=0.5
TEXT 856 456 Left 0 !.param Rx=1/((1-2*Vout/Vin)*Ts/(2*L))
TEXT 1736 408 Left 0 ;bjs
TEXT 856 480 Left 0 !.param Ry=Rs*Vin/Vramp
TEXT 8 480 Left 0 ;slope comp
TEXT 856 504 Left 0 !.param gm1=-D*D*Ts/(2*L)
TEXT 856 528 Left 0 !.param gm2=Vout*Vramp/(Vin*Vin*Rs)
TEXT 856 552 Left 0 !.param Icmn2=Vc/Rs - Vout*(1-Vout/Vin)*Ts/(2*L) - Vramp*D/Rs
TEXT 360 464 Left 0 !.step param Vin list 10 8 6 4


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I found the following issues while working on the attached circuit.
There are easy work arounds for all of these, but they are something
to be aware of. (Some may be caused by operator error.) Brad

1.)
B4 and B6
I had to use two sources in series instead of just one because the
expression would not evaluate correctly if one of the terms goes to
zero in the ac analysis. If one term goes to zero, the whole
expression evaluates to "-1.#INFTdB" even if the other term is not
zero.

2.)
B2
B2 would not evaluate correctly when using the expression "I=i(B3)*v
(duty)". This was fixed by adding V9 to sense the current of B3 and
using the expression "I=i(V9)*v(duty)".

3.)
Dividing by zero in .param
Dividing by zero in a .param expression appears to be ignored and
gives the result as if dividing by one. For example:
.param Ry=Rs*Vin/Vramp
is effectively
.param Ry=Rs*Vin
when Vramp is zero.

Note: The circuit contains two models for the current mode
controlled continuous conduction buck converter. One uses non-linear
equations, and the other is linearized. They give the same ac
results now that I worked around the issues.

Version 4
SHEET 1 2160 1048 WIRE 96 80 288 80 WIRE 352 208 352 272 WIRE 352
272 560 272 WIRE 560 272 560 208 WIRE 352 128 352 80 WIRE 560 128
560 80 WIRE 560 80 608 80 WIRE 288 80 352 80 WIRE 608 80 784 80 WIRE
352 272 288 272 WIRE 560 272 1248 272 WIRE 288 272 208 272 WIRE 1440
128 1440 80 WIRE 1440 80 1504 80
WIRE 1440 208 1440 272 WIRE 1504 80 1552 80 WIRE 96 272 96 208 WIRE
96 128 96 80
WIRE 1248 80 1248 128 WIRE 1248 272 1248 208 WIRE 208 304 208 272
WIRE 208 272 96 272 WIRE -96 448 -96 400 WIRE -96 400 -48 400 WIRE -
96 592 -96 528 WIRE 160 400 192 400 WIRE 1024 80 1248 80 WIRE 560 -
208 560 -240 WIRE 560 -240 688 -240
WIRE 1360 -240 1360 -192 WIRE 1360 -48 1008 -48 WIRE 560 -48 560 -
128 WIRE 768 -112 768 -48 WIRE 768 -48 560 -48 WIRE 768 -192 768 -
240 WIRE 880 -240 1008 -240 WIRE 1296 -240 1360 -240 WIRE 688 -240
768 -240 WIRE 96 400 160 400

WIRE 880 -192 880 -240 WIRE 768 -240 880 -240 WIRE 880 -112 880 -48
WIRE 768 -48 880 -48 WIRE -48 400 16 400 WIRE 560 -48 416 -48 WIRE
416 -48 272 -48 WIRE 208 -16 208 -48 WIRE 208 -48 96 -48 WIRE 1360 -
112 1360 -48
WIRE 1568 -192 1568 -240 WIRE 1568 -240 1632 -240 WIRE 1568 -112
1568 -48 WIRE 1632 -240 1760 -240 WIRE 1824 -192 1824 -240 WIRE
1824 -240 1888 -240 WIRE 1824 -112 1824 -48 WIRE 1888 -240 1936 -240
WIRE 1760 -240 1760 -48 WIRE 1760 -48 1824 -48 WIRE 1152 -240 1216 -
240 WIRE 416 -128 416 -48 WIRE 416 -208 416 -240 WIRE 416 -240 368 -
240 WIRE 96 -240 96 -208

WIRE 96 -128 96 -48 WIRE 272 -96 272 -48 WIRE 272 -176 272 -240 WIRE
272 -48 208 -48 WIRE 272 -240 96 -240 WIRE 368 -240 272 -240
WIRE 1008 -192 1008 -240 WIRE 1008 -240 1072 -240 WIRE 1008 -112
1008 -48 WIRE 1008 -48 880 -48 WIRE 1632 592 1632 528 WIRE 1632 448
1632 400 WIRE 1632 400 1680 400 WIRE 1680 400 1712 400 WIRE 1808 592
1808 528 WIRE 1808 448 1808 400 WIRE 1808 400 1856 400 WIRE 1856 400
1888 400 WIRE 864 80 944 80

FLAG 288 80 act FLAG 608 80 cmn FLAG 288 272 pas FLAG 1440 272 0
FLAG 1504 80 duty FLAG 208 304 0 FLAG -96 592 0 FLAG 160 400 vc FLAG
688 -240 cmn2 FLAG -48 400 vc1 FLAG 208 -16 0 FLAG 1568 -48 0
FLAG 1632 -240 duty2 FLAG 1888 -240 duty3 FLAG 368 -240 act2 FLAG
1632 592 0

FLAG 1680 400 test1 FLAG 1808 592 0 FLAG 1856 400 test2
SYMBOL bv 1440 112 R0 SYMATTR InstName B1
SYMATTR Value V=(v(cmn)-v(pas))/(v(act)-v(pas)+1u) SYMBOL bi 352 128
R0

SYMATTR InstName B2
SYMATTR Value I=i(v9)*v(duty) SYMBOL bi2 560 128 R0

SYMATTR InstName B3
SYMATTR Value I=v(vc)/Rs - (v(act)-v(pas))*v(duty)*(1-v(duty))*Ts/
(2*L) SYMBOL Misc&#92;&#92;battery 96 112 R0

WINDOW 123 24 132 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2
SYMATTR Value {Vin}
SYMBOL Misc&#92;&#92;battery 1248 112 R0 SYMATTR InstName V3

SYMATTR Value {Vout} SYMBOL voltage -96 432 R0 WINDOW 123 24 132
Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value2 AC 1 SYMATTR InstName V4
SYMATTR Value {Vc}
SYMBOL ind 928 96 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0
SYMATTR InstName L1 SYMATTR Value {L}

SYMATTR SpiceLine Rser=0 SYMBOL bi2 560 -208 R0 SYMATTR InstName B44
SYMATTR Value I=v(vc1)/Rs SYMBOL res 752 -208 R0 SYMATTR InstName Rx
SYMATTR Value {Rx}
SYMBOL ind 1200 -224 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56
VBottom 0 SYMATTR InstName L2 SYMATTR Value {L}
SYMATTR SpiceLine Rser=0 SYMBOL bv 0 400 R270 WINDOW 0 32 56 VTop 0
WINDOW 3 -32 56 VBottom 0 SYMATTR InstName B5
SYMATTR Value V=Vramp*v(duty) SYMBOL res 864 -208 R0 SYMATTR
InstName Ry

SYMATTR Value {Ry}
SYMBOL Misc&#92;&#92;battery 1360 -208 R0 SYMATTR InstName V5

SYMATTR Value {Vout} SYMBOL bv 1568 -208 R0 SYMATTR InstName B4
SYMATTR Value V=v(cmn2)/Vin SYMBOL bv 1824 -208 R0 SYMATTR InstName
B6

SYMATTR Value V=-v(act2)*Vout/(Vin*Vin) SYMBOL bi 416 -208 R0
SYMATTR InstName B7
SYMATTR Value I=i(v1)*D SYMBOL voltage 1056 -240 R270 WINDOW 0 32 56
VTop 0

WINDOW 3 -32 56 VBottom 0 SYMATTR InstName V1 SYMATTR Value 0
SYMBOL Misc&#92;&#92;battery 96 -224 R0 WINDOW 123 21 130 Left 0

WINDOW 39 0 0 Left 0 SYMATTR InstName V6 SYMATTR Value {Vin} SYMBOL
bi 272 -176 R0 SYMATTR InstName B8
SYMATTR Value I=v(duty3)*Icmn2 SYMBOL bi2 1008 -192 R0 SYMATTR
InstName B10

SYMATTR Value I=(gm1+gm2)*v(act2) SYMBOL Misc&#92;&#92;battery 1632 432 R0
SYMATTR InstName V7
SYMATTR Value {Icmn2}
SYMBOL Misc&#92;&#92;battery 1808 432 R0 SYMATTR InstName V8

SYMATTR Value {Ry}
SYMBOL voltage 768 80 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 -32 56
VBottom 0 SYMATTR InstName V9 SYMATTR Value 0

TEXT 856 408 Left 0 !.param Rs=0.1 L=1.5u Ts=5u TEXT 358 388 Left
0 !;tran 1m uic
TEXT 360 416 Left 0 !;op
TEXT 536 384 Left 0 !.nodeset v(cmn)=2.5

TEXT 536 408 Left 0 !.ac dec 25 1 10meg TEXT -136 -232 Left 0 ;Small-
Signal Model
TEXT -136 88 Left 0 ;Nonlinear&#92;nAveraged Model
TEXT 856 384 Left 0 !.param Vin=10 Vout=2.5 Vramp=1u D=Vout/Vin
TEXT 856 432 Left 0 !.param Vc=0.5
TEXT 856 456 Left 0 !.param Rx=1/((1-2*Vout/Vin)*Ts/(2*L))
TEXT 1600 680 Left 0 ;bjs
TEXT 856 480 Left 0 !.param Ry=Rs*Vin/Vramp
TEXT 8 480 Left 0 ;slope comp
TEXT 856 504 Left 0 !.param gm1=-D*D*Ts/(2*L)
TEXT 856 528 Left 0 !.param gm2=Vout*Vramp/(Vin*Vin*Rs)
TEXT 856 552 Left 0 !.param Icmn2=Vc/Rs - Vout*(1-Vout/Vin)*Ts/
(2*L) - Vramp*D/Rs TEXT 360 464 Left 0 !.step param Vin list 10 8 6 4




---

--- In LTspice@..., mathias.borcke@i... wrote:

Hello *

I want to do distortion analysis in the audio frequency range. This

means I

would like to simulate down to 0.00x percent distortion products.
Frequently I end up with ca. 1% distortion just measuring the

oscillator

itself.
The amount of distortion increases with the number of cycles that I
simulate. (see example circuit below)
I have made some progress (with a real circuit) with adjusting the

settings

in the Spice pane of the Control Panel, however I do not really

know what in

detail these entries mean.
--> Can you give me a short description of the adjustment options?
--> Does anyone know a better way to simulate distortion? (DC-

transfer

analysis ?)

Hello Mathias
you have to switch off any kind of compression mode in
Control Panel -> Compression . Please click all buttons off.
Next choose a time step of <= 1us, e.g. .TRAN 0 10ms 0 1us.
The result then looks very promising.

I recommend to move the .Fourier statement to its own command line,
otherwise you will not get the comfortable selection box for
the .TRAN statement.

I have attached another thread about fourier analysis with LTSPICE
where I was involved in the past.

Best Regards
Helmut

Attachement:
-----------

"fred bartoli" <toto@...> schrieb im Newsbeitrag
news:3dd929e8$0$18267$626a54ce@......

Helmut Sennewald <HelmutSennewald@...> a écrit dans le

message :

arb8bm$gl156$1@......

"Piercarlo Boletti" <piercarloboletti@...> schrieb im

Newsbeitrag

news:1flugn4.1vu8bay1lzya00N%piercarloboletti@......

Hi!

I need a little help to understand use of FFT in spice, but

particularly

focused on SwitcherCad-LTspice.

I use that simulator to esteem intrinsic distortion of a certain

number

of basic circuit use in low-frequency or audio application. FFT

appear

to be optimal to get a quick glimpse of the overall distortive

impact
of

the topologies under testing

BUT

There is a litte problem with the - or simply my - use of FFT

itself.

More closely: disturbed from costantly too high values of

distortion

i've tried a junk meausure of a pure sine generator driving a

pure
load

resistor. The output expected, a pure fundamental, was not

obtained;
on

i'ts place was displayed a nastly distorted signal - very

distorted

indeed.

What is wrong?

Hello Pierecarlo,

when you do discrete Fourier Transform(DFT,FFT), you only take a
snapshot from a signal. The discrete Fourier transform then
delivers the fourier coeffients of a signal which is equivalent
to an infinity number of concatenated snapshots.

What do we learn from that?
If your snapshot does not contain exactly full periods of all your
frequencies(signal), there will be a big discontinuity in the

assumed

concatenuated signal from one snapshot(window) to the next.
As a result, your FFT gives you very broad peaks.

That's were the FFT-windows come into play. They force the signal
and there derivatives to zero at the ends of your snapshot

(window).

This helps but is by far not as good as a well choosen time frame
which contains only full periods of your signal.

FFT versus DFT
--------------
The result from the FFT is the same as from the DFT. The only
difference is the faster calculation with the FFT. This is
especially true when the number of data points is a power of 2.
Then a lot of similar calculations can be avoided by the clever
FFT algorithm.

Resolution and max. frequency
-----------------------------
The frequency resolution of the DFT is 1/time.
If you have a FFT-time of 100ms, you get 10Hz resolution.

The max. frquency you get is fmax = 0.5*FFT_data_points/time .
Example: time=100ms, data points=16384 -> fmax about 800kHz.

Best Result of FFT with SwitcherCADIII
--------------------------------------
1. Select .TRAN for exactly a full number of periods of your
lowest freuency in the signal.
2. All compression modes off in the menue
Tools -> Control Panel -> Compression
3. FFT Settings: Window none
Data points; 16384 points or more, depends on up to what
frequency you want to look.


You will reach sidebands below than -120dB and often they are
below -150dB which is more than adequate for your ears. :-)


Best Regards
Helmut

Just one minor adjustment :
The signal must *not* contain full periods but full periods *minus*

one

sample time (see what happens at boundaries when connecting the

samples).

Using full periods leads to some still significant leakages that

might
hide

useful details.

Hello Fred,
thank you very much for this correction. It is really important
as you said that the last data point in the taken window is not
the one which is the first data point of the the next window.
This is as more important as less data points we use.


Example with a window of one period and 8 data points.


o o o o
o | | o o
o | | | | o o
o o | | | | | | o o
| | | | | | | |
------------------------------------------------------
0 1 2 3 4 5 6 7


The whole thing is a bit more complicated due to the .TRAN analysis
which is normally set to another timestep then used by the FFT.
SwitcherCADIII then has to nterpolate the data points used for the
FFT.

Hey, a great idea came into my mind.
Select the time step for simulation to span/16384 for a intended
FFT with 16384 data points. The time step looked very odd,
but the result has been impressive. Now I have achieved -180dB !!!
spurious signal level for a pure sine source. Thanks Mike too for
the high numerical precision.

One way to deal with that is to apply windowing to ensure both

extremity
of

the curve will nicely join but this still leads to some leakages.

This
also

apply only in the case you can post process the waveform, and I

don't know

whether SWCad can do that or not.

The other way is, provided you anticipate the FFT number of points,

to set

the total simulation time to
N*SigPeriod*(1-1/(2*FFTDataPoints)) i.e. N*SigPeriod - 1 sample

time

Also let enough time for the transients to settle i.e. provide a

non null

start recording time to the .TRAN

I agree, this is the next pitfall, because we always have bandwidth
limiting elements (C, L) which lead to startup transients in the
.TRAN simulation.

Best Regards
Helmut

开云体育

Mike,

Thanks for the quick response! LTspice is a fantastic program, and
you provide best support of any software! You are providing a
tremendous service.

Brad


--- In LTspice@..., Panama Mike <panamatex@y...> wrote:

Brad,

The measured current in B sources appears to have reversed

polarity.

Thanks for the report...I've fixed the error and will update the
web next week.

My high speed connection just came back up so I was able to update
the web leaving for the weekend. Just do Tools=>Sync Release to
get version 2.03f which has the behavioral current source complex
ammeter reading the correct sign.

--Mike

---

Brad,

The measured current in B sources appears to have reversed polarity.

Thanks for the report...I've fixed the error and will update the
web next week.

My high speed connection just came back up so I was able to update
the web leaving for the weekend. Just do Tools=>Sync Release to
get version 2.03f which has the behavioral current source complex
ammeter reading the correct sign.

--Mike

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Brad,

The measured current in B sources appears to have reversed polarity.

Thanks for the report. Your's right, the current is reported reversed
from the direction it's really going in the behavioral current
sources, but it is going in the right direction as far as the rest
of the circuit goes. It's just the internal ampmeter reads the wrong
sign, not the the current is going in the wrong direction. I've
fixed the error and will update the web next week. In the meanwhile,
just plot -I(B1) for to plot the correct answer or rely on external
current monitoring.

--Mike


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