Hoa,

My goal, or rather my professor's goal, is to
look for potential new tools to replace the
cumbersome Hspice and Avanti Awaves combo.
The level 3 model is only the model used in
one particular class. Using our level 49 BSIM
model for the Op Amp I gave, I was able to
obtain almost identical results from LTspice
and Hspice. So I will definitely recommend
LTspice to my professor and hope to convince
to drop the level 3 model.

Oh, well, there's some merit to MOS3 for
educational purposes as it's more intuitive
and was an important step in the IC design/
simulation history. It depends what the class
is about.

To that end, I think I've got the MOS3 problem
fixed. The fix is not yet in the general release
which is still Version 2.03f of May 23, 2003.
It's going to take another week or two before the
MOS3 fix make it into the general release because
that will also include the new sparse matrix solver.

But in the meanwhile, please try out this executable:



It should be able to solve most any MOS3 circuit you
give it. The Jacobian error w.r.t ETA is corrected
in that version. This is version 2.03g alpha. It is
a 2,834,432 byte download of the LTspice executable
only, not the full distribution. You can either keep
your former executable as a backup or use the Sync
Release Menu command to bring you back to the official
general release version.

I *think* the small signal AC analysis is done
correctly in this fixed version, but that aspect is
not well tested yet. The basic DC and TRAN behavior
of it looks pretty good -- it runs the regression
tests I have now in record time since it has a more
accurate Jacobian.

I'm actually a graduate student at Stanford
University. My goal, or rather my professor's goal,
is to look for potential new tools to replace the
cumbersome Hspice and Avanti Awaves combo.

As you're in the neighborhood, please feel free to
stop by Linear Tech. Corp. headquarters in Milpitas
where I'm located if you want to go over any other
issues you have or need addressed.

--Mike

__________________________________
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Yahoo! Calendar - Free online calendar with sync to Outlook(TM).

On Wed, 11 Jun 2003 08:47:41 +0200, you wrote:

I should simulate a fluorescent lamp. However I have some difficulties to find a correct model, because of nevative resistance of the lamp. While sinusoidal current rises up , voltage falls down to take power costant.
Has anybody ideas how to simulate this?

Hehe. *The* man to speak to (or he was, at the end of 2001) on
the subject of fluorescent lamp models is John P. Verboncoeur,
Associate Professor in Residence, Dept. Nuclear Engineering,
Department of Electrical Engineering and Computer Sciences,
University of California, Berkeley, CA 94720-1770 USA

He can be reached at: mailto:johnv@... and at
mailto:johnv@... or 510-642-3477 and 510-642-6330
(fax).

An expert at modeling these things, he told me that the full
understanding requires at least 2 spatial and one time dimension
of PDEs coupled to at least 6-dimensional ODEs, along with
radiation transport and atomic interactions (the cutting edge.)
But these lamps have been built for a long time without that
degree of understanding.

For example, you can do a fair amount with global rate equations
which assume spatially averaged densities for the charged
particles and neutral atoms and molecules, excited and
metastable states. There is an intermediate text by Lieberman
and Lichtenberg, Principles of Plasma Discharges and Materials
Processing, published by John Wiley and Sons, which does a good
treatment of the fundamentals of discharges, global models,
collisions, and DC and RF discharges.

None of this deals with ballast, of course. It's just the lamp
part. Regarding drive, there are two kinds in common use, now.
Traditional fluorescent lamps use a magnetic core and remain at
60 Hz (or 50 Hz in Europe.) Compact fluorescent do operate at a
higher drive frequency, using an eletronic ballast. These work
by converting the wall frequency to DC, then use an inverter to
produce 20-50 kHz driving current signal.

The low frequency lamps operate as DC discharges (Townsend
discharges, as they were once called.) The high frequency
variety operate like RF discharges, in that the period of the
current drive is faster than the decay time of the plasma, so
the conductivity never drops to zero. This has other benefits,
like reduced flicker. Ion transit time is L / v_i, where L is
the length of the lamp and v_i is the ion velocity.

The tube surface is remarkably cold, compared to the gas plasma,
itself. The mercury readily condenses there, plating the
surface, but there is an equilibrium between condensing and
evaporating mercury. It does not take a very high vapor
pressure to run the lamp, but this is why fluorescents cannot be
used in extremely low temperatures.

Anyway, I don't have any ready models for you. But if you
should need any refinement for ones you do find (if the ones you
have don't predict experiment well) then I'd suggest contacting
John Verboncoeur for suggestions about where to do -- and he may
also be a good contact to point you to someone who has developed
Spice models, already.

Best of luck,
Jon

Mike,

Thanks for your exhaustive response. I'm actually a graduate student
at Stanford University. My goal, or rather my professor's goal, is to
look for potential new tools to replace the cumbersome Hspice and
Avanti Awaves combo. The level 3 model is only the model used in one
particular class. Using our level 49 BSIM model for the Op Amp I
gave, I was able to obtain almost identical results from LTspice and
Hspice. So I will definitely recommend LTspice to my professor and
hope to convince to drop the level 3 model. :)

Thanks again,

Hao

开云体育

Mike,

I liked your idea a lot better since it's more intuitive, so I gave
it a try and it works fine. I had tried it previously without the R=
but, of course, that doesn't work!

Steve

Thanks Mike,

I assume I'm supposed to post any replies to the group.

It looks like you're a night person like me!

I ended up doing something very similar. I used a behavioral current
source. In the simple example below I put 5 volts on the control
lead, node 002. Therefore it emulates a resistor that is 5 x 5k + 1
or 25001 ohms.

If you look at the voltage and current in B1, you can calculate
Requiv = 10/0.4ma = 25,000 ohms which agrees with the concept in the
previous paragraph.

You'll notice that I addressed your concern by adding a 1 in the
denominator so it won't go to zero for positive control voltages.

Thanks again,

Steve




Version 4
SHEET 1 880 680
WIRE -16 160 -16 80
WIRE 16 448 16 416
WIRE 16 336 16 288
WIRE 16 288 144 288
WIRE 144 288 144 336
WIRE 144 416 144 448
WIRE -288 160 -288 80
WIRE -288 80 -16 80
FLAG -16 240 0
FLAG 16 448 0
FLAG 144 448 0
FLAG -288 240 0
SYMBOL voltage 16 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 128 320 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL voltage -288 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 10
SYMBOL bi -16 160 R0
SYMATTR InstName B1
SYMATTR Value I=(V(n001)/(1+5k*V(n002)))
TEXT -50 506 Left 0 !.tran 1m

Steve,

Does anyone have a model for a voltage controlled resistor?

With a current version of LTspice, you can just
replace the value of the resistor with an
equation of the form R=<expression>.

Here's a netlist that gives an example:

* Intrinsic arbitrary resistor
V1 x 0 sine(1 .1 1K)
R1 1 0 R=3K*V(x)
I1 0 1 1m
.tran 3m
.end

The underlying implementation is a Norton
equivalent circuit, so you might need to be
careful that the resistance doesn't go
through zero.

--Mike

__________________________________
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Yahoo! Calendar - Free online calendar with sync to Outlook(TM).

Does anyone have a model for a voltage controlled resistor?

It shouldn't be too difficult to do, but no sense reinventing the
wheel!

Thanks,

Steve

--- In LTspice@..., Panama Mike <panamatex@y...> wrote:

Helmut,

I am in a discussion about modeling of an opamp with
MOS Level-3 transistors in the YAHOO-LTSPICE-Group.
After some xperiments, I asked Hao for the result of
a simple inverter simulation (Hao_inv.cir,
transistors.txt). The result of I_drain(M1) looks
quite different in HSPICE. Could you test it with
other simulators. At the moment there is some
belief that the LTSPICE Level=3 model is not correct.
Please put your answer into the YAHOO-LTSPICE group.

Yes, there is a problem for mos3 ETA being very small.
It looks like it works fine if ETA is around 1.(which
is where MOS3 was designed to operate) and it's okay
if ETA is zero. But other than that it's something of
an odd ball the fixes to the Berkeley device apperar
to be non-standard. I'm close to a solution on that,
in that I've identified one error in the way the Jacobian
is computed in Berkeley spice, but haven't finised it
to work with all permutations of the other mos3
parameters.

Hello Mike,
thank you very much for your clear explanations.

Another question:
I haven't seen any minor update since more than a week.
Is LTSPICE still alive?

Yes, of course. I've been swamped preparing a new release
that contains two solvers, ...

I am glad to hear that you are still working on improvements of
LTSPICE.

It could end up close to 6MB instead of 3MB.

The size doesn't matter. Reliability and functionality is the key.

Best Regards
Helmut

Helmut,

I am in a discussion about modeling of an opamp with
MOS Level-3 transistors in the YAHOO-LTSPICE-Group.
After some xperiments, I asked Hao for the result of
a simple inverter simulation (Hao_inv.cir,
transistors.txt). The result of I_drain(M1) looks
quite different in HSPICE. Could you test it with
other simulators. At the moment there is some
belief that the LTSPICE Level=3 model is not correct.
Please put your answer into the YAHOO-LTSPICE group.

Yes, there is a problem for mos3 ETA being very small.
It looks like it works fine if ETA is around 1.(which
is where MOS3 was designed to operate) and it's okay
if ETA is zero. But other than that it's something of
an odd ball the fixes to the Berkeley device apperar
to be non-standard. I'm close to a solution on that,
in that I've identified one error in the way the Jacobian
is computed in Berkeley spice, but haven't finised it
to work with all permutations of the other mos3
parameters.

BTW, LTspice does okay with practical MOS3 models.
MOS3 is something of an obsolete MOS type, so I don't
know if I'm going to be able to spend enough time on
it to completely fix it for all models. The device
is nolonger of real use. At least I don't know of
any IC's designed today with mos3 device models.

Another question:
I haven't seen any minor update since more than a week.
Is LTSPICE still alive?

Yes, of course. I've been swamped preparing a new release
that contains two solvers, one with a new sparse matrix
package that can solve those pathological PSpice style
opamps models like Stuart Brorson's OP177A opamps circuits
with no problem. I expect that release out in less than
two weeks. BTW, the new version is quite a lot larger
executable, over 4Megbytes. Even larger if I compile
in support for Pentium 4 instructions(since it still
needs a copy of the AMD code for backward compatiblity)
It could end up close to 6MB instead of 3MB.

I'll anounce here when this version is availible.

--Mike



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Yahoo! Calendar - Free online calendar with sync to Outlook(TM).

--- In LTspice@..., "Hao Fu" <fuhao@y...> wrote:

--- In LTspice@..., "Helmut Sennewald"
<helmutsennewald@y...> wrote:

Hello Hao,
this inverter has absolutely no problem in LTSPICE. May be you

have

selected some "bad" options in the control panel of LTSPICE.

Please

reset all options to its default values.
Control Panel->SPICE->Reset fo Defaults
Control Panel->Hacks-> Reset to Defaults
You must use the latest LTSPICE version 2.03f.
Then run the simulation and plot V(out) and Id(M1).
Please tell me your findings compared to HSPICE or even better

send

me the plot from HSPICE of V(out) and Id(M1).
email: HelmutSennewald@t...
I have attached my/your model file transistors.txt.

Best Regards
Helmut

I did the comparison. The ids look quite different between the 2
runs. Anyway, I have put the plots from Hspice run in the Files
folder, it's named inverter.ps.

Ok, the inverter experiment didn't fail completely in my runs

either.

I did get all the voltages and currents. But the Spice Error Log
still complains about Gmin stepping failures, that is what bothered
me.

Thanks,

Hello Hao,
thanks for the PDF-file. Indeed the current looks different.
I have written now a message to "Panama Mike"(Mike Engelhardt from
Linear Technology) and asked him to check the MOS model. Let's see
what he will tell us.

Best Regards
Helmut

--- In LTspice@..., "Helmut Sennewald"
<helmutsennewald@y...> wrote:

Hello Hao,
this inverter has absolutely no problem in LTSPICE. May be you have
selected some "bad" options in the control panel of LTSPICE. Please
reset all options to its default values.
Control Panel->SPICE->Reset fo Defaults
Control Panel->Hacks-> Reset to Defaults
You must use the latest LTSPICE version 2.03f.
Then run the simulation and plot V(out) and Id(M1).
Please tell me your findings compared to HSPICE or even better send
me the plot from HSPICE of V(out) and Id(M1).
email: HelmutSennewald@t...
I have attached my/your model file transistors.txt.

Best Regards
Helmut

I did the comparison. The ids look quite different between the 2
runs. Anyway, I have put the plots from Hspice run in the Files
folder, it's named inverter.ps.

Ok, the inverter experiment didn't fail completely in my runs either.
I did get all the voltages and currents. But the Spice Error Log
still complains about Gmin stepping failures, that is what bothered
me.

Thanks,

Hao

--- In LTspice@..., "Hao Fu" <fuhao@y...> wrote:

Helmut,

I tried to run a simple inverter with that level 3 model, it has

the

same convergence problem. Here is the error message:

Hello Hao,
this inverter has absolutely no problem in LTSPICE. May be you have
selected some "bad" options in the control panel of LTSPICE. Please
reset all options to its default values.
Control Panel->SPICE->Reset fo Defaults
Control Panel->Hacks-> Reset to Defaults
You must use the latest LTSPICE version 2.03f.
Then run the simulation and plot V(out) and Id(M1).
Please tell me your findings compared to HSPICE or even better send
me the plot from HSPICE of V(out) and Id(M1).
email: HelmutSennewald@...
I have attached my/your model file transistors.txt.

Best Regards
Helmut

Included file MOS models transistors.txt
----------------------------------------

* Level 3 BSIM MOSFET Models
.MODEL NMOS NMOS LEVEL=3 PHI=0.7 TOX=9.5E-09 XJ=0.2U TPG=1
+ VTO=0.7 DELTA=8.8E-01 LD=5E-08 KP=1.56E-04
+ UO=420 THETA=2.3E-01 RSH=2.0E+00 GAMMA=0.62
+ NSUB=1.40E+17 NFS=7.20E+11 VMAX=1.8E+05 ETA=2.125E-02
+ KAPPA=1E-01 CGDO=3.0E-10 CGSO=3.0E-10
+ CGBO=4.5E-10 CJ=5.50E-04 MJ=0.6 CJSW=3E-10
+ MJSW=0.35 PB=1.1

* Level 3 BSIM MOSFET Models
.MODEL PMOS PMOS LEVEL=3
+ PHI=0.7
+ TOX=9.5E-09
+ XJ=2E-7
+ TPG=-1
+ VTO=-0.95
+ DELTA=2.5E-01
+ LD=7E-08
+ KP=4.8E-05
+ UO=130
+ THETA=2.0E-01
+ RSH=2.5E00
+ GAMMA=0.52
+ NSUB=1.0E17
+ NFS=6.50E11
+ VMAX=3.0E05
+ ETA=0.02
+ KAPPA=8.0
+ CGDO=3.5E-10
+ CGSO=3.5E-10
+ CGBO=4.5E-10
+ CJ=9.50E-04
+ MJ=0.5
+ CJSW=2E-10
+ MJSW=0.25
+ PB=1

* Simple inverter measurement
.include 'transistors.txt'

* include this to use mwaves on the output!
.options itl6=400
.temp 25

.global vdd gnd

.param vdd = 3.5V
+ cload = 0.1fF
+ os = 3.2u
+ cm = 2.5
+ wn = 16u
+ wp = 40u

* circuit. This is in netlist format.
vdd vdd gnd 'vdd'
vcm in gnd dc 'cm'
*vos1 cm os1 dc 'os/2'
*vos2 os2 cm dc 'os/2'
M1 out in gnd gnd nmos W='wn' L='0.5u'
+AD='1.5u*wn' PD='2*(1.5u+wn)' AS='1.5u*wn' PS='2*

(1.5u+wn)'

M2 out in vdd vdd pmos W='wp' L='0.5u'
+AD='1.5u*wp' PD='2*(1.5u+wp)' AS='1.5u*wp' PS='2*

(1.5u+wp)'

Cload out gnd 'cload'

* Simulation
.op
.dc vcm 0 3.5 0.01
*.step lin param os 3u 3.5u 0.1u

.end

--- In LTspice@..., "irf610" <ejb9535@u...> wrote:

Hi,

Does somebody know where to find a model for a tv flyback

tranformer?

OR mabe know how to build one. My knowledge in magnetic material is

quite limited so tv flyback transformer is somewhat complicated for
me.

Check out SMPS Simulation with SPICE 3 by Steve M. Sandler. It has a
good section on magnetics modeling, as well as other sections on
modeling buck and flyback regulators.

- John

Hi,

Does somebody know where to find a model for a tv flyback tranformer?

OR mabe know how to build one. My knowledge in magnetic material is quite limited so tv flyback transformer is somewhat complicated for me.

Helmut,

I tried to run a simple inverter with that level 3 model, it has the
same convergence problem. Here is the error message:

Direct Newton iteration failed to find .op point. (Use ".option
noopiter" to skip.)
Starting Gmin stepping
Gmin = 10
Gmin = 1.07374
Gmin = 0.115292
Gmin = 0.0123794
Gmin = 0.00132923
vernier = 0.5
vernier = 0.25
Gmin = 0.000387166
vernier = 0.125
vernier = 0.0625
vernier = 0.03125
Gmin = 0.000361149
vernier = 0.015625
vernier = 0.0078125
Gmin = 0.000355558
vernier = 0.0104167
vernier = 0.00520833
vernier = 0.00694444
Gmin = 0.000351038
vernier = 0.00925925
vernier = 0.00462963
vernier = 0.00231481
vernier = 0.00115741
vernier = 0.000578703
Gmin = 0.000348007
vernier = 0.000289352
vernier = 0.000144676
vernier = 7.23379e-005
vernier = 3.6169e-005
vernier = 1.80845e-005
vernier = 9.04224e-006
vernier = 4.52112e-006
vernier = 2.26056e-006
vernier = 1.13028e-006
vernier = 5.6514e-007
Gmin = 0.000348007
vernier = 2.8257e-007
vernier = 1.41285e-007
vernier = 7.06425e-008
vernier = 3.53212e-008
vernier = 1.76606e-008
vernier = 8.83031e-009
vernier = 4.41516e-009
vernier = 2.20758e-009
vernier = 1.10379e-009
vernier = 5.51894e-010
Gmin = 0.000348007
vernier = 2.75947e-010
vernier = 1.37974e-010
vernier = 6.89868e-011
vernier = 3.44934e-011
vernier = 1.72467e-011
vernier = 8.62335e-012
vernier = 4.31168e-012
vernier = 2.15584e-012
vernier = 1.07792e-012
vernier = 5.38959e-013
Gmin = 0.000348007
vernier = 2.6948e-013
vernier = 1.3474e-013
vernier = 6.73699e-014
vernier = 3.3685e-014
vernier = 1.68425e-014
vernier = 8.42124e-015
vernier = 4.21062e-015
Gmin = 0
Gmin stepping failed

Starting source stepping
Source Step = 0.25%
Source Step = 2.75%
Source Step = 5.25%
Source Step = 7.75%
Source Step = 10.25%
Source Step = 12.75%
Source Step = 15.25%
Source Step = 17.75%
Source Step = 20.25%
Source Step = 22.75%
Source Step = 25.25%
Source Step = 27.75%
Source Step = 30.25%
Source Step = 32.75%
Source Step = 35.25%
Source Step = 37.75%
Source Step = 40.25%
Source Step = 42.75%
Source Step = 45.25%
Source Step = 47.3125%
Source Step = 47.4541%
Source Step = 47.4639%
Source Step = 47.4736%
Source Step = 47.4746%
vernier = 1.49012e-008
Source Step = 47.4746%
vernier = 1.42109e-014
Source stepping failed

And this is my simple inverter:

* Simple inverter measurement
.include 'transistors.txt'

* include this to use mwaves on the output!
.options itl6=400
.temp 25

.global vdd gnd

.param vdd = 3.5V
+ cload = 0.1fF
+ os = 3.2u
+ cm = 2.5
+ wn = 16u
+ wp = 40u

* circuit. This is in netlist format.
vdd vdd gnd 'vdd'
vcm in gnd dc 'cm'
*vos1 cm os1 dc 'os/2'
*vos2 os2 cm dc 'os/2'
M1 out in gnd gnd nmos W='wn' L='0.5u'
+AD='1.5u*wn' PD='2*(1.5u+wn)' AS='1.5u*wn' PS='2*(1.5u+wn)'
M2 out in vdd vdd pmos W='wp' L='0.5u'
+AD='1.5u*wp' PD='2*(1.5u+wp)' AS='1.5u*wp' PS='2*(1.5u+wp)'
Cload out gnd 'cload'

* Simulation
.op
.dc vcm 0 3.5 0.01
*.step lin param os 3u 3.5u 0.1u

.end


Could there be something wrong with LTspice's modeling with ETA?

With best regard,

Hao

--- In LTspice@..., "Hao Fu" <fuhao@y...> wrote:

Thanks Helmut.

I tried the .options gmin=1e-11 directive, but it doesn't seem to
take any effect. The error message is exactly the same as before.

Hello Hua,
thanks for the whole circuit file. I tried it and I had some success
after a few modifications.

I added the following lines to the main circuit file:
-----------------------------------------------------
* Replace the line Rs2 ... with a DC-feedback path, but AC signals
have to be still shorted for open loop gain testing.
I think this is a better way for open loop testing.
*Rs2 pre_in2 in2 1k
Rfb out in2 10MEG
Cfb gnd in2 1

Next step was to increase the iteration limit:
.OPTIONS itl6=400
By the way, this was the only option which really helped.

Modify the subcircuit:
It still failed until I reduced the overall open loop gain within the
subcircuit "opamp" definition. It is the new line there:
Rifb load out 1e9
The maximum value for Rifb depends on the load resistance applied to
the opamp ouput. I have seen open loop gains of 120dB depending on
load resistance.
What open loop gain do you see with HSPICE and my modifications?

It would be very interesting to simulate a simple NMOS and PMOS
Level-3 inverter with HSPICE and LTSPICE and compare them.
I am interested in the DC operating point and the AC gain of this
circuit. This will give us confidence that the MOS models are
calculated equally in both simulators. Can you do that for me?

" Test Circuit
"
" Vcc -------------------o
" ____|___
" | 0.1mA | current source
" |________|
" |
" -|10MEG|--o------- out
" | _____|
" 1 | | |
" ---||--o--| | single transistor
" |AC| | |_____
" | |
" Gnd--o-----------------o
"
|AC| is a .AC source with 1V amplitude


Summary:
--------
We still haven't found really the reason for the difference about
convergence. The next step should be the comparison of the simple MOS
inverter. Depending on that result we can give Mike Engelhardt the
direction where to improve LTSPICE.

Best Regards
Helmut

Opamp model with the new Rifb ... line.

.subckt opamp in_pos in_neg out vdd gnd
* The current mirror
Rref bias0 gnd 40.2k
x0 ss bias0 vdd vdd p1_5 w=200u
x13 bias0 bias0 vdd vdd p1_5 w=200u
* The diff pair
x1 load1 in_neg ss ss p1_5 w=200u
x2 load2 in_pos ss ss p1_5 w=200u
* The load
x7 load1 load1 gnd gnd n2_0 w=50u
x8 load2 load1 gnd gnd n2_0 w=50u
* The second stage
x11 out bias0 vdd vdd p1_5 w=400u
x12 out load2 gnd gnd n1_5 w=130u
* Compensation
rcoup load2 int0 1k
ccoup int0 out 3p
Rifb load2 out 1e9
.ends opamp

I'm pasting my analysis file below:


* Open Loop Differential Gain
* model statement.
.include 'transistors.txt'
.include 'opamp1.sp'

.OPTIONS Gmin=1e-12
.OPTIONS gminsteps=100

*.OPTIONS Gmin=1e-12
*.OPTIONS gminsteps=100
.OPTIONS itl6=400

.global vdd gnd
.param cload = 0.5pF
+ vdd = 5
+ os = 3.2u
+ deltas = 1
+ cm = 2.5

* Netlist
vdd vdd gnd 'vdd'
vcm cm gnd dc 'cm'
vos1 cm os1 dc 'os/2'
vos2 os2 cm dc 'os/2'
vin1 pre_in1 os1 dc 0 ac 'deltas/2'
vin2 os2 pre_in2 dc 0 ac 'deltas/2'

Rs1 pre_in1 in1 1k

*Rs2 pre_in2 in2 1k
Rfb out in2 10MEG
Cfb gnd in2 1

Cload out gnd 'cload'

* The OP-AMP
x1 in1 in2 out vdd gnd opamp

* Simulation
.ac lin 100 10 1000
.op

.end

Thanks Helmut.

I tried the .options gmin=1e-11 directive, but it doesn't seem to
take any effect. The error message is exactly the same as before.

I'm pasting my analysis file below:


* Open Loop Differential Gain
* model statement.
.include 'transistors.txt'
.include 'opamp1.sp'

.OPTIONS Gmin=1e-12
.OPTIONS gminsteps=100

.global vdd gnd
.param cload = 0.5pF
+ vdd = 5
+ os = 3.2u
+ deltas = 1
+ cm = 2.5

* Netlist
vdd vdd gnd 'vdd'
vcm cm gnd dc 'cm'
vos1 cm os1 dc 'os/2'
vos2 os2 cm dc 'os/2'
vin1 pre_in1 os1 dc 0 ac 'deltas/2'
vin2 os2 pre_in2 dc 0 ac 'deltas/2'

Rs1 pre_in1 in1 1k
Rs2 pre_in2 in2 1k
Cload out gnd 'cload'

* The OP-AMP
x1 in1 in2 out vdd gnd opamp

* Simulation
.ac lin 100 10 1000
.op

.end


Here is the missing PMOS model definition:

* Level 3 BSIM MOSFET Models
.MODEL PMOS PMOS LEVEL=3
+ PHI=0.7
+ TOX=9.5E-09
+ XJ=2E-7
+ TPG=-1
+ VTO=-0.95
+ DELTA=2.5E-01
+ LD=7E-08
+ KP=4.8E-05
+ UO=130
+ THETA=2.0E-01
+ RSH=2.5E00
+ GAMMA=0.52
+ NSUB=1.0E17
+ NFS=6.50E11
+ VMAX=3.0E05
+ ETA=0.02
+ KAPPA=8.0
+ CGDO=3.5E-10
+ CGSO=3.5E-10
+ CGBO=4.5E-10
+ CJ=9.50E-04
+ MJ=0.5
+ CJSW=2E-10
+ MJSW=0.25
+ PB=1

Thanks again for your help.

Hao



--- In LTspice@..., "Helmut Sennewald"
<helmutsennewald@y...> wrote:

--- In LTspice@..., "Hao Fu" <fuhao@y...> wrote:

I found out what's wrong with my model definition. It appears

that

the ETA parameter of the level 3 spice model can not be less than
1, even though the default is 0.

Hello Hao,
I tried your *Stack of 3, nmos" in a simple common source circuit

and

the result looks ok, even for any ETA, e.g. ETA=2.125e-2 like in

your

NMOS .model.

I'm wondering what this parameter
really represents and whether the current range for this parameter
is > as originally intended. I greatly appreciate any answer.

Try Google for the LEVEL=3 MOS model. Try Google with:
nmos eta static feedback

ETA modifies the threshold voltage as a linear function of Vds.
Vth = Vbi - k*ETA*Vds

Back to your error message:

Fatal Error: doAnalyses: Iteration limit reached

I assume that the command line:
.OPTIONS Gmin=1e-11 or Gmin=1e-10
would solve your problem. It looks like a "simple" convergence
problem, but I couldn't try that because the .model PMOS definition
is missing in your attached subcircuit model.
Please post this PMOS model too and the circuit file .asc also.

Best Regards
Helmut

--- In LTspice@..., "Hao Fu" <fuhao@y...> wrote:

I found out what's wrong with my model definition. It appears that
the ETA parameter of the level 3 spice model can not be less than
1, even though the default is 0.

Hello Hao,
I tried your *Stack of 3, nmos" in a simple common source circuit and
the result looks ok, even for any ETA, e.g. ETA=2.125e-2 like in your
NMOS .model.

I'm wondering what this parameter
really represents and whether the current range for this parameter
is > as originally intended. I greatly appreciate any answer.

Try Google for the LEVEL=3 MOS model. Try Google with:
nmos eta static feedback

ETA modifies the threshold voltage as a linear function of Vds.
Vth = Vbi - k*ETA*Vds

Back to your error message:

Fatal Error: doAnalyses: Iteration limit reached

I assume that the command line:
.OPTIONS Gmin=1e-11 or Gmin=1e-10
would solve your problem. It looks like a "simple" convergence
problem, but I couldn't try that because the .model PMOS definition
is missing in your attached subcircuit model.
Please post this PMOS model too and the circuit file .asc also.

Best Regards
Helmut

I found out what's wrong with my model definition. It appears that
the ETA parameter of the level 3 spice model can not be less than 1,
even though the default is 0. I'm wondering what this parameter
really represents and whether the current range for this parameter is
as originally intended. I greatly appreciate any answer.

Thanks,

Hao


--- In LTspice@..., "Hao Fu" <fuhao@y...> wrote:

Hi all,

I'm trying to simulate a very simple 3 stage differential amplifier
in LTSpice. The design works well in Hspice. However, when I try to
run it under LTSpice, I got the following output in the Spice error
log:

Starting Gmin stepping
Gmin = 10
Gmin = 1.07374
Gmin = 0.115292
Gmin = 0.0123794
Gmin = 0.00132923
Gmin = 0.000142725
vernier = 0.5
vernier = 0.25
vernier = 0.125
vernier = 0.0625
vernier = 0.03125
vernier = 0.015625
vernier = 0.0078125
Gmin = 9.13439e-005
vernier = 0.00390625
vernier = 0.00195313
vernier = 0.000976563
vernier = 0.000488281
vernier = 0.000244141
vernier = 0.00012207
vernier = 6.10352e-005
vernier = 3.05176e-005
vernier = 1.52588e-005
vernier = 7.62939e-006
Gmin = 9.13439e-005
vernier = 3.8147e-006
vernier = 1.90735e-006
vernier = 9.53674e-007
vernier = 4.76837e-007
vernier = 2.38419e-007
vernier = 1.19209e-007
vernier = 5.96046e-008
vernier = 2.98023e-008
vernier = 1.49012e-008
vernier = 7.45058e-009
Gmin = 9.13439e-005
vernier = 3.72529e-009
vernier = 1.86265e-009
vernier = 9.31323e-010
vernier = 4.65661e-010
vernier = 2.32831e-010
vernier = 1.16415e-010
vernier = 5.82077e-011
vernier = 2.91038e-011
vernier = 1.45519e-011
vernier = 7.27596e-012
Gmin = 9.13439e-005
vernier = 3.63798e-012
vernier = 1.81899e-012
vernier = 9.09495e-013
vernier = 4.54747e-013
vernier = 2.27374e-013
vernier = 1.13687e-013
vernier = 5.68434e-014
vernier = 2.84217e-014
vernier = 1.42109e-014
vernier = 7.10543e-015
Gmin = 9.13439e-005
vernier = 5.32907e-015
Gmin = 0
Gmin stepping failed

Starting source stepping
Source Step = 3.0303%
Source Step = 3.03031%
vernier = 9.53674e-007
Source Step = 3.0303%
vernier = 9.09495e-013
Source stepping failed

Fatal Error: doAnalyses: Iteration limit reached


Here is my opamp definition:

* |--Non-Inverting Input
* | |--Inverting Input
* | | |--Output
* | | | |--positive supply
* | | | | |--negative supply
.subckt opamp in_pos in_neg out vdd gnd
* The current mirror
Rref bias0 gnd 40.2k
x0 ss bias0 vdd vdd p1_5 w=200u
x13 bias0 bias0 vdd vdd p1_5 w=200u
* The diff pair
x1 load1 in_neg ss ss p1_5 w=200u
x2 load2 in_pos ss ss p1_5 w=200u
* The load
x7 load1 load1 gnd gnd n2_0 w=50u
x8 load2 load1 gnd gnd n2_0 w=50u
* The second stage
x11 out bias0 vdd vdd p1_5 w=400u
x12 out load2 gnd gnd n1_5 w=130u
* Compensation
rcoup load2 int0 1k
ccoup int0 out 3p
.ends opamp


And this is my model definition:

*** Stack of 3, nmos
.subckt n1_5 drain gate source sub w=15u
M2a drain gate srca sub nmos W='w' L='0.5u'
+AD='1.5u*w' PD='2*(1.5u+w)' AS='1.5u*w' PS='2*(1.5u+w)'
M2b srca gate srcb sub nmos W='w' L='0.5u'
+AD=0 PD=0 AS='1.5u*w' PS='2*(1.5u+w)'
M2c srcb gate source sub nmos W='w' L='0.5u'
+AD=0 PD=0 AS='1.5u*w' PS='2*(1.5u+w)'
.ends n1_5

*Stack of 3, pmos
.subckt p1_5 drain gate source well w=15u
M2a drain gate srca well pmos W='w' L='0.5u'
+AD='1.5u*w' PD='2*(1.5u+w)' AS='1.5u*w' PS='2*(1.5u+w)'
M2b srca gate srcb well pmos W='w' L='0.5u'
+AD=0 PD=0 AS='1.5u*w' PS='2*(1.5u+w)'
M2c srcb gate source well pmos W='w' L='0.5u'
+AD=0 PD=0 AS='1.5u*w' PS='2*(1.5u+w)'
.ends p1_5

* Stack of 4, nmos
.subckt n2_0 drain gate source sub w=15u
M2a drain gate srca sub nmos W='w' L='0.5u'
+AD='1.5u*w' PD='2*(1.5u+w)' AS='1.5u*w' PS='2*(1.5u+w)'
M2b srca gate srcb sub nmos W='w' L='0.5u'
+AD=0 PD=0 AS='1.5u*w' PS='2*(1.5u+w)'
M2c srcb gate srcc sub nmos W='w' L='0.5u'
+AD=0 PD=0 AS='1.5u*w' PS='2*(1.5u+w)'
M2d srcc gate source sub nmos W='w' L='0.5u'
+AD=0 PD=0 AS='1.5u*w' PS='2*(1.5u+w)'
.ends n2_0

* Level 3 BSIM MOSFET Models
.MODEL NMOS NMOS LEVEL=3 PHI=0.7 TOX=9.5E-09 XJ=0.2U TPG=1
+ VTO=0.7 DELTA=8.8E-01 LD=5E-08 KP=1.56E-04
+ UO=420 THETA=2.3E-01 RSH=2.0E+00 GAMMA=0.62
+ NSUB=1.40E+17 NFS=7.20E+11 VMAX=1.8E+05 ETA=2.125E-02
+ KAPPA=1E-01 CGDO=3.0E-10 CGSO=3.0E-10
+ CGBO=4.5E-10 CJ=5.50E-04 MJ=0.6 CJSW=3E-10
+ MJSW=0.35 PB=1.1


I have a strong suspicion that LTSpice doesn't like my model
definitios. But given the scarce error messages, I'm unable to

trace

down any further. I would greatly appreciate anyone who can help me.

Thanks,

Hao