--- In LTspice@..., "Hao Fu" <fuhao@y...> wrote:
Thanks Helmut.
I tried the .options gmin=1e-11 directive, but it doesn't seem to
take any effect. The error message is exactly the same as before.
Hello Hua,
thanks for the whole circuit file. I tried it and I had some success
after a few modifications.
I added the following lines to the main circuit file:
-----------------------------------------------------
* Replace the line Rs2 ... with a DC-feedback path, but AC signals
have to be still shorted for open loop gain testing.
I think this is a better way for open loop testing.
*Rs2 pre_in2 in2 1k
Rfb out in2 10MEG
Cfb gnd in2 1
Next step was to increase the iteration limit:
.OPTIONS itl6=400
By the way, this was the only option which really helped.
Modify the subcircuit:
It still failed until I reduced the overall open loop gain within the
subcircuit "opamp" definition. It is the new line there:
Rifb load out 1e9
The maximum value for Rifb depends on the load resistance applied to
the opamp ouput. I have seen open loop gains of 120dB depending on
load resistance.
What open loop gain do you see with HSPICE and my modifications?
It would be very interesting to simulate a simple NMOS and PMOS
Level-3 inverter with HSPICE and LTSPICE and compare them.
I am interested in the DC operating point and the AC gain of this
circuit. This will give us confidence that the MOS models are
calculated equally in both simulators. Can you do that for me?
" Test Circuit
"
" Vcc -------------------o
" ____|___
" | 0.1mA | current source
" |________|
" |
" -|10MEG|--o------- out
" | _____|
" 1 | | |
" ---||--o--| | single transistor
" |AC| | |_____
" | |
" Gnd--o-----------------o
"
|AC| is a .AC source with 1V amplitude
Summary:
--------
We still haven't found really the reason for the difference about
convergence. The next step should be the comparison of the simple MOS
inverter. Depending on that result we can give Mike Engelhardt the
direction where to improve LTSPICE.
Best Regards
Helmut
Opamp model with the new Rifb ... line.
.subckt opamp in_pos in_neg out vdd gnd
* The current mirror
Rref bias0 gnd 40.2k
x0 ss bias0 vdd vdd p1_5 w=200u
x13 bias0 bias0 vdd vdd p1_5 w=200u
* The diff pair
x1 load1 in_neg ss ss p1_5 w=200u
x2 load2 in_pos ss ss p1_5 w=200u
* The load
x7 load1 load1 gnd gnd n2_0 w=50u
x8 load2 load1 gnd gnd n2_0 w=50u
* The second stage
x11 out bias0 vdd vdd p1_5 w=400u
x12 out load2 gnd gnd n1_5 w=130u
* Compensation
rcoup load2 int0 1k
ccoup int0 out 3p
Rifb load2 out 1e9
.ends opamp
I'm pasting my analysis file below:
* Open Loop Differential Gain
* model statement.
.include 'transistors.txt'
.include 'opamp1.sp'
.OPTIONS Gmin=1e-12
.OPTIONS gminsteps=100
*.OPTIONS Gmin=1e-12
*.OPTIONS gminsteps=100
.OPTIONS itl6=400
.global vdd gnd
.param cload = 0.5pF
+ vdd = 5
+ os = 3.2u
+ deltas = 1
+ cm = 2.5
* Netlist
vdd vdd gnd 'vdd'
vcm cm gnd dc 'cm'
vos1 cm os1 dc 'os/2'
vos2 os2 cm dc 'os/2'
vin1 pre_in1 os1 dc 0 ac 'deltas/2'
vin2 os2 pre_in2 dc 0 ac 'deltas/2'
Rs1 pre_in1 in1 1k
*Rs2 pre_in2 in2 1k
Rfb out in2 10MEG
Cfb gnd in2 1
Cload out gnd 'cload'
* The OP-AMP
x1 in1 in2 out vdd gnd opamp
* Simulation
.ac lin 100 10 1000
.op
.end
