On Wed, Feb 5, 2025 at 02:06 AM, eewiz wrote:
I am pretty sure this has nothing to do with version 24.1.1.? I think LTspice has always behaved this way - going back at least as far as LTspice IV and probably earlier.
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After running the sim, nothing changes outside the block, still ground on one side of the resistor and V(n030) on the other side connected to the RTN hierarchical connector.
Inside the block, the RTN hierarchical connector still says "Click to plot V(n030)" but, the net connected to that RTN hierarchical connector now says "This is ground."
Bee careful here.? When looking at a local schematic, LTspice doesn't know that this net is going to be used as something other than ground, so it calls it "ground" when displaying that schematic.? You might think that is incorrect, but LTspice doesn't know (can't tell) without knowing where the external connections go.? On a local view of a lower-level schematic, it can not tell - especially because it might be used different ways if more than one higher-level schematic calls it.
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I think the same thing would happen if you drew a multi-level hierarchical design without a ground symbol on any of the lower-level schematics.? Let's say you took node "ABC" on a lower-level schematic, and tied its pin directly to node 0 on the top-level schematic.? When examining that schematic in isolation in the schematic editor, LTspice does not know that this net will actually become node 0.? So it labels the net "ABC" even though it will be "0".? The local schematic view is never the full expanded picture.? It can only look locally.
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The resistor outside the block has one end connected to ground and its other end also connected to ground through a hierarchical connector named RTN.
That observation is incorrect.? The net that LTspice labels "ground" in the lower-level schematic, is not actually ground when it becomes connected to the higher-level schematic.? Therefore the resistor outside the block is
NOT connected to ground on both ends.? It must not disappear from the netlist, because it really is there!
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Unfortunately we have two domains, and you need to be careful not to mix them.? There is the local picture - looking at the lower-level schematic - and there is the global picture after "expansion" and connections are made.? At the end of the day, the only "real" one is after expansion.? But it is not possible to "see" that while looking at a lower-level schematic in the schematic editor.? That view doesn't "know" what the external connections will be.
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The same exact thing happens all the time when examining lower-level schematics in the schematic editor.? If you hover over a net that goes to an Input, Output, or Bi-Direct pin (one of the ones with a box drawn around the name), LTspice can only display its LOCAL net name, even though that is NOT the real name of the net.? Think of it as only a temporary net name, used until connections are made to the next higher-level schematic.??When you use that lower-level schematic in your hierarchy, that net's name changes.? But in the local view of that schematic, LTspice doesn't know what that name will be.? So it can only name it (incorrectly? not really) with the net name that you drew on that one schematic.
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You might say, "Can't LTspice examine where the net goes in the next higher level, and show the right names after expansion?"? The answer is No, because that lower-level schematic might be called (used) 3 times, maybe even in 3 different higher schematics, meaning that the 3 instances of this net actually have 3 distinct net names.? LTspice can't show all of them.? It is not one single net, it is 3 distinct nets.? In one of those circuit calls, that pin might connect to node 0.? When looking at this lower-level schematic, it would be both correct and incorrect to say that the net is "ground".? The only reasonable thing LTspice can do, is show what its apparent net name would be, in total isolation.
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That is why your view of your lower-level schematic calls the net "ground", even though the net ends up NOT being ground after connections are made and the netlist is expanded.? "Ground" is its temporary name, subject to revision during netlist expansion.
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Since LTspice's ground (GND) (node 0) is a perfect superconductor that never drops any voltage, there can never be any current through that resistor because it is grounded on both ends.
Yes, that would be true if N003 was actually ground.? But it is not.? Do not think that N030 = 0.
A resistor grounded on both ends is removed from the netlist hence, it shows no "plot my current" arrow when pointed at.
A resistor grounded on one end with the other end unconnected or connected to an open wire, is also removed from the netlist.
Neither resistor's current nor the open net's voltage can be plotted.
None of that happens in your case with hierarchy because node N030 is
NOT node 0 or "ground".
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I urge you to be very careful about making these observations.? You have a tendency to make incorrect assumptions and jump to inflexible conclusions that are incorrect, and then you stick to those wrong conclusions.? I'm sorry to be critical, but I have seen this happen over and over.? Keep an open mind and don't close your options.
1. If routing ground out of a hierarchical schematic, be absolutely sure to remove all of the triangular (label 0) ground symbols from the interior of that hierarchical block and physically connect any nets that may have been disconnected by those ground symbol removals.
That can be a rule to follow, but it is not necessary.? You do need to understand that your external connections to that net (to every net in the schematic) take precedence.? If you connect that net to something that isn't ground, then the net won't be grounded - no matter how "wrong" it may look to you when examining just the lower level schematic in isolation.
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It is actually reasonable to draw a lower-level schematic, where a net is called "ground" locally (using the triangle symbol), but also goes to an I/O pin (with a box around it).? That ENABLES you to selectively "override that ground".? If the higher-level schematic doesn't connect to the pin, it remains ground.? If the higher-level schematic connects it to +150 V, that net becomes not-grounded and has +150 V on it.? Think of it as a feature you didn't realize was there.
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As I wrote earlier (in another message), this is extremely helpful when importing external netlists into LTspice.? Some vendors write their SPICE models with signals going to node 0 that you would rather not be grounded.? Before LTspice, I had to re-write their SPICE models to disconnect them from ground.? It was a PITA.? Now, LTspice handles it automatically.? Within the context of the subcircuit, the node appears to be node 0.? But when the subcircuit is called and connections are made to the next-higher level in the hierarchy, that net changes to something other than node 0.? It's wonderful.? LTspice does the right thing.
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As far as I am aware, in other SPICE programs (well, only a few that I've tried), node 0 was always ground, no matter where it was used.? LTspice is the only program I know that has this wonderful feature.
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I would not be surprised to find that all nodes "0" within a sub-circuit would need to be renamed to something like "00" to ensure that LTspice does connect all those nodes together but does not sumarilly connect that net to ground.
That is the hard way to do it.? That would be what I used to do, except that I had to use a nodename like 9999 or "AltGnd".? Many other SPICE programs treat nodes 00 and 000 as identical to node 0.
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Or maybe not, maybe LTspice treats node 0 within a sub-circuit cell differently then it treats the triangular (label 0) ground symbol within a sub-circuit block.
If I understand what you're saying, that is correct.? Inside a lower-level schematic or netlist, LTspice treats node 0 as "maybe ground", which
can be overridden by an external connection when the schematics and subcircuits are expanded.
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On the other hand, if you suggest that subcircuits in Netlist form behave differently than lower-level schematics, that is incorrect.? It treats them the same.? They are the same.
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Andy
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