Are you emulating real switches or perfect instantaneous switches?
If you are emulating real switches the your conclusions are correct in that a slightly less that 25% waveform is the most efficient. I'm in the process of creating my own QSD and it will use 20% waveform.
The reason is fairly simple, real switches do not turn on and off instantaneously, if you have switches turn on while another turns from on to off, the timing difference will cause the switches to have a short circuit for a brief period. By having less than 25% on the waveform you are insuring that the switches are all off before turning one on, and thereby avoid that brief short.
At 08:45 AM 10/27/2005, Phil Covington wrote:
Hi Tony,
Let me take a look at this and report back.
I reran the simulation with a 4 switch QSD using two signal
integrating capacitors. I am taking the 4 switch QSD with 4
integrating capacitors and 50% clock duty cycle as the reference
(0dB). Here is what I have so far:
4SW4 QSD is the 4 switch qsd circuit with 4 signal integrating
capacitors. I(Q) and /I(/Q) are summed with an op amp. This is like
the SDR-1000 QSD.
2SW2 QSD is the 2 switch qsd circuit with 2 signal integrating caps.
This would be like SR V5
4SW2 QSD is the 4 switch qsd circuit with 2 signal integrating caps.
The caps are selected twice each cycle like SR V4.
50% duty cycle clock:
4SW4 QSD -> 0 dB (reference)
2SW2 QSD -> -5.86 dB
4SW2 QSD -> -5.62 dB
25% duty cycle clock:
4SW4 QSD -> +2.45 dB
2SW2 QSD -> -3.26 dB
4SW2 QSD -> -2.63 dB
15% duty cycle clock:
4SW4 QSD -> +2.14 dB
2SW2 QSD -> -3.45 dB
4SW2 QSD -> -2.22 dB
The 4SW2 QSD seems to have the least loss at around 12 - 15% duty
cycle clock.
73 de Phil N8VB
--- In softrock40@..., "Tony Parks" <raparks@c...> wrote:
Hi Phil,
The question I just ask about gain reduction as a function of phase
clock
skew is not the right question to ask. What we really are
interested in is
the gain from RF input to demodulated signal output. In the case of
CW I
would think this would just be the vector sum of the I and Q signals.
Another important question is if clock skew causes undesired signal
response.
73,
Tony KB9YIG
----- Original Message -----
From: "Phil Covington" <p.covington@g...>
To: <softrock40@...>
Sent: Wednesday, October 26, 2005 1:04 PM
Subject: [softrock40] QSD Models
Hi all,
I've placed some results of simulation of a two switch and four switch
QSD circuit on my blog at:
Check it out if you are interested in the QSD circuits.
73 de Phil N8VB
Yahoo! Groups Links
Yahoo! Groups Links
Cecil Bayona
KD5NWA
www.qrpradio.com
I fail to see why doing the same thing over and over and getting the same results every time is insanity: I've almost proved it isn't; only a few more tests now and I'm sure results will differ this time ...
