开云体育

I guess that depends on what you consider as minimal
and if you are modeling an ideal resistor or a more
realistic one.

For example: on the first image is the plot of voltage
angle at the load (port 2 in this case), calculated from the
S21 file if the load is an ideal 50Ω.
The black trace is for a model of a 10K resistor with 50fF
of capacitance (reasonable value, according to Vishay for a
0805 capacitor) also into an ideal 50Ω.

[image: image.png]

The second image shows the same plot but this
time instead of an ideal 50Ω termination at port2,
I used the measured values for port2.
Not much of a change.

[image: image.png]

Last image is the port2 as measured, on a Smith chart (zoomed in quite a
bit).

[image: image.png]


Keep in mind that the calibration was done with
DIY "standards" and jig all made from cheap SMA
connectors from AliExpress, where the center
pin moves if you tighten the connectors enough.
DYT also from China with unknown properties.
Quite a sloopy setup.








On Tue, 16 Feb 2021 at 20:47, Roger Need via groups.io <sailtamarack=
[email protected]> wrote:

Dragan,

Thank you for clarifying what you did on your tests. I took a look at the
.s2p file that you posted and see that you get the same large S21 phase
shift that I got in my tests. I posted my plot of your S21 data below.
For a tiny SMD resistor like the one you used the phase shift should be
minimal (at least on the lower frequencies.). The S21 magnitude loss is
very close to what it should be for a 10K resistor but that phase shift
will give a lower R value and indicate reactance that isn't there if I
understand this correctly. Do you agree?

I also did a conversion from serial to parallel impedance and your S11
measurement was surprising close to 10K ohms. For a VNA designed for 50
ohm system impedance this was very good. Plot attached.

Roger