On Sat, Oct 26, 2024 at 07:04 AM, wn4isx wrote:
Do you have a fast oscilloscope (preferably DSO)? And actually verify the spikes?
Try more low ESR capacitance on V+/V- lines, conssder adding low value inductor with capacitor [LC] filter circuit between V+ and high current switches.
Taming EMC (electromagnetic compatibility) issues is part black magic.
?
I think that is a spike seen in simulation.? Not in hardware.? I don't think he built it yet.? But I may be wrong.
?
As you know, sometimes simulations go beyond what's reasonable and show effects you can't actually see when you build it.? But if you have good models, your simulations should come pretty close.
?
John23, what is the pulsewidth of that glitch?? Is it wide enough to be worth worrying about?? If it is something like 10 ps wide, you might argue that it won't go anywhere.? Simulations have bandwidth from DC to light (well, almost).? Real circuits do not.? Wires get in the way.
?
The spike might come from capacitive coupling from Gate to Drain in one or both MOSFETs.? All MOSFETs have that and it can't be avoided, but different MOSFETs have different amounts of it so you can choose MOSFETs with lower Cgd.? When their Gate pin toggles, the dv/dt couples to the Drain which is still briefly a high impedance.? You can slow the dv/dt at the Gate, which might help.? You can reduce the voltage that gets coupled to the Drain with a capacitive voltage-divider (that is, add capacitors Drain-to-ground) which might help.? Or you can slow it further downstream in the direction of the Vg2 node.? I am not certain this is the mechanism by which the glitch happens, but it is a likely one.? I did not simulate it yet.? You (john23) have this on your computer already, and you can simulate it and witness first-hand where and how the coupling happens.? I urge you to do that.? Be an engineer and investigate how it gets there, and what you can do about it.
?
Andy
?
?
