开云体育

*** Fixated? It's the processor I have, Bill. I didn't choose it. - Jerry

You seem very fixated on a processor that can't achieve your goals then... Dr. William J. Schmidt - K9HZ J68HZ 8P6HK ZF2HZ PJ4/K9HZ VP5/K9HZ PJ2/K9HZ VP2EHZ Owner - Operator Big Signal Ranch – K9ZC

Well. It's all a matter of priorities, isn't it? What must happen every loop? What can be deferred? Right now, it defers updating the spectrum - and probably, running the loop - while you tune. The

“throw them out and assess their impact on the performance.” Seems like the right thing to do… but then what? Dr. William J. Schmidt - K9HZ J68HZ 8P6HK ZF2HZ PJ4/K9HZ VP5/K9HZ PJ2/K9HZ VP2EHZ

There has been a lot of code added in loop() that wasn't there to begin with, and all of that take time. If you want, perhaps there are things within that loop that you can live without. If that's the

Software issues. Not my thing. Dr. William J. Schmidt - K9HZ J68HZ 8P6HK ZF2HZ PJ4/K9HZ VP5/K9HZ PJ2/K9HZ VP2EHZ Owner - Operator Big Signal Ranch – K9ZC Staunton, Illinois Owner – Operator Villa

*** The problem with a slow display is that it slows down the whole system. Each swing of the main loop happens after the display updates. When you are tuning around, the audio pauses between clicks.

Well… I don’t know how much yet because I don’t even have the gerbers. Based on the encoder boards (it will be about the same size)… the board will be $0.50 or less… and the connectors are

How much for a copy?? Any plans to sell assembled version?? Or just post Gerbers?

TBH, I don't put a tremendous stock in reviews.? I really only use the book as a reference, it works well for that. It puts too much emphasis on using Verilog as a test bench vs true FPGA

The higher the frequency, the faster the display updates, but the higher the SPI frequency is into the HF band causing harmonics. That is the wrong direction! See how low you can go and still have a

*** You sure? Wouldn't a faster SPI give faster display updates? And therefore less chunky tuning? - Jerry, KF6VB

You should make that divisor as big as possible up to the point that the display still works.... makes the SPI as slow as possible and creates less noise. Dr. William J. Schmidt - K9HZ J68HZ 8P6HK

*** Indeed. I just added the following line near the top of setup(): SPI.setClockDivider( SPI_CLOCK_DIV2 ); I'm not sure if it's faster or not. It does compile, and the radio works. - Jerry, KF6VB

I don’t have boards yet for the display driver upgrade so that will be at least a week. I have something special in mind for the board so that it plugs in to the display connector on the Main board

If you want to read a little bit about the ARM/FPGA board… here is a summary link: MKR VIDOR 4000 - Arduino | Mouser <https://www.mouser.com/new/arduino/arduino-mkr-vidor-4000/> Correction: It’s a

You can test that... Dr. William J. Schmidt - K9HZ J68HZ 8P6HK ZF2HZ PJ4/K9HZ VP5/K9HZ PJ2/K9HZ VP2EHZ Owner - Operator Big Signal Ranch – K9ZC Staunton, Illinois Owner – Operator Villa Grand

Bill, When will you be accepting orders for the driver board and updated RF boards?? Do you have your automated ordering site on-line yet?? Dave Fine, W0DF

I bought one to play with it. The chips on the board (ARM Cortex M0 and the Cyclone 15 FPGA) are in production and will be for some time even though that developmental board won’t. That just means

Tried that chip and its similar in design to the 74HC125, as a true “low output impedance” bus driver with Schmitt trigger input. As you would expect, you see the same type of behavior as the