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In another topic, Matthew D'Entremont said he was looking for a PD55003 LDMOS model. I searched the group's archives but do not find any files with "PD55003" in the filename or description or (cleartext) contents. If it is in a .zip file, it would not find it unless the name or description includes that text. Andy

Is there a non-linear model for Mini Circuits PHA-13HLN driver PA that someone can share with me?

Hi all - anyone seen or been bitten by this? I'm working on a middling-sized circuit, nothing fancy, all passives and library ADI opamps, inamps and diff drivers. Implementing a little gain and (as you'd expect from me) some filtering functions, including some series LC traps close to the inputs. It's one of those circuits that's on the edge of not finding a DC op point (24.0.12 on this work machine, 24.1.x deffo not ready for salaried work IMHO). Series traps are from signal nodes to ground. So there's a capacitor on the branch between that node and ground. So in principle it cannot participate in any DC op point calculations. But... I get to the point where, slowly dropping down the inductor's series resistor (most tests with internal but external seemed similar), I would cross a threshold where it couldn't find an op point. Quite abruptly; for instance, Rs >=65 gave an op point, Rs <=64 and lower did not. (alternate solver; didn't test normal). So, clearly, the NAM must have some DC path across that cap. Tried changing the Gmin setting from default 1E-12 to 1E-14. Success! Now all realistic configurations give me an operating point. This is something that could be fixed (hi @mstokowski and @mborn) - by making sure that Gmin==0 across any capacitor that's not otherwise set up to be different, _just_ during the op point search. Of course the DC solver needs to be robust to hanging branches so there might need to be some topology trim/prep, solving a slightly different matrix (the caps in series case will probably be irritating). So not trivial, just simple... I have a sneaking feeling that some of my older op point troubles could have been fixed up this way. Another way of doing this would be to have a flag for a capacitor to explicitly set Re (shunt admittance) to zero - but that's much more work for the user. Better for the code to do it inherently (perhaps with a setting choice box). Of course 24.1.5+ might already have fixed this, I can't try that until at least this evening. Hope this is interesting and relevant -- K PS (1) how do you stop the .log file from popping up at the end of each sim now, annoying and (2) where did the little display of the key for which .step plotted to which color trace go?

Hello, I am interested to verify/replicate through simulation using LTspice the plot: 15 Typ. gate charge -> VGS = f(Qgate);I D = 25 A pulsed, parameter: VDD for this N-channel MOSFET from Infineon: IAUC50N08S5L096 I took the model from Infineon site: SimulationModels Do you know if exists any ltspice simulation file example for this thing on how to do correctly? I tried a simulation, but I do not know if the simulation set-up is pretty good/correct. Please see: /g/LTspice/files/Temp/Gate_Charge_Characteristic_Mosfet.zip And to have Qgate for time axis I need to plot time*Ix(M1:D), where Ix(M1:D) is the current through drain of the mosfet, right? But then how to make in such a way to have the range for x axis of the VGS plot 0nC...24nC? Thank you.

Hi LTspice Group, I have simulated a filter which is a cascaded of two LC low-pass filters. I get the Bode plot Magnitude in dB versus frequency and phase versus frequency. However, I need to display the magnitude in dBuV versus frequency. dB is just a value but dBuV is a value with reference 1uV. I tried few things but no one worked. Is there a way to show dBuV vs Frequency? Has anyone tried it before? LCLC filter is uploaded. Comments are appreciated! Ray

I am trying to make a better Jumper: The Lib Jumper does NOT separate net names (in VXVII, at least) I’m stupidly missing *something* in creating a new device “Unknown subcircuit called in: xu1 a b” Suggestions? Thanks, Dave

Hi, I am trying to figure out a way to plot gm/Id for a transistor within LTspice. I am using as a starting point the schematic in the example MOSFET parameter sweep, MOS_gm_gmb_gds_ro.asc , within Examples&#92;Examples&#92;Educational&#92;MOSFET parameter sweep&#92; . In short, I am stepping the W/L and biasing sources and running .OP and .AC LIST 1 analysis . The example computes gm, gmb, gds, using the small-signal values from the AC analysis. To plot gm/Id I would need to obtain the bias current of the NMOS transistor, either from the DC current through the voltage sources or through the device itself. Is there a way to refer to this current from the waveform viewer, maybe a trick I am missing ? The Spice Log file lists the device operating point for just one iteration, so I don't see how to extract the bias information for the steps, which is obviously being computed prior to the each AC analysis. In short, given a sequence of AC analysis, how can I obtain/extract the bias point information for the circuit/devices, and if possible refer/use it within the waveform view when plotting ? Helmut, can you help ? Mike, are you out there ? Fellow users, any ideas/work arounds ? Thanks in advance for any help!

Did someone upload such a circuit earlier this year? I saved, wherever it came from, but now I can't find it. -- Best wishes John Woodgate RAYLEIGH Essex OOO-Own Opinions Only www.woodjohn.uk If something is true: * as far as we know - it's science *for certain - it's mathematics *unquestionably - it's religion Virus-free.www.avg.com

Hi, I'm sure this has been asked before but in searching I couldn't find anything that addressed my issue, so apologies if this is a duplicate. As an exercise I'm modeling the 741 op-amp internal structure (from this reference) but I can't get the lateral PNP to behave as expected (Q13A/B). I get the expected 730uA through the reference current mirror, and the expected ~20uA through the Q20 mirror. But through Q13B I should be sourcing 0.75*Iref and I'm only getting ~12uA; similarly through Q13A i should be sourcing 0.25*Iref and I'm only getting 75pA. Model statements used for all parts are in the schematic. The only difference between Q13 and the standard PNP used is the saturation current Is changed from 10fA (standard) to 7.5fA (Q13B) and 2.5fA (Q13A). Apparently I'm missing something else about how this stage is supposed to function, seemingly with Q13. Any ideas to get this working?

Hello,I have imported the tsmc Pdk 180nm shown bellow in the ltspice model. however in the 1:01:06 moment of the video they somehow managed in the menu to get the channel width of the mosfet. Where I import the spice model as is and I cant change the W of the mosfet . How did they do it in Ltspice ? /g/LTspice/files/Temp/pmos_vds.asc 1:01:06 https://www.youtube.com/watch?v=GE6KhOM9fGo&t=3664s https://sanjayvidhyadharan.in/Downloads/tsmc_180_nm/tsmc018.lib

I was working with the recently linked AD PV Cell sim. It uses a MUR460 library diode, multiple in series, to simulate the cell/string’s forward voltage. The default series resistance seems too high, per plotted I/V curve. The diode’s parameter string includes “rs=0.0384”, and I want to vary that to adjust the curve to the panel I want to simulate. The model adds a multiplier to the diode, “N=15”, which I successfully changed to “N={Ns}” so I could vary the number of cells. I tried adding an override of rs by “N={N} Rs={Rser}”, but the second term throws an “unrecognized” fault. Right-clicking the diode symbol doesn’t offer any route to setting any terms. I imagine I could use a default “D” diode and modify all of the params, but I don’t see any way to copy the LONG string listed in “Pick new diode”. Is there a better (i.e. working) way to override the internal params? Thanks, Dave

Trying to get this opamp model to work. I keep getting errors. I know it has to do with the "TABLE" lines, but not sure how to fix. Model was pulled from OnSemi's website. File is posted in the temp section as NCS2001_test.zip

Hi, I am trying to create a duty cycle that kind of continuously varying like in a 200ms simulation I want a duty cycle start from 0.01 to 0.99 (approximately 0.01 Duty increase per 2 ms). How can I do this I am really struggling with it . Thanks

Hi All How can one restore the Classic Menu in LTSpice Version 24.1.6? Regards ik

Hi, I am trying to understand how MPPT works in a buck converter with resistive load by doing an LTSpice simulation. I have a PV model which works very accurately with a current sink load. And it works perfectly as in figure below (I can also change irradiance and its very accurate with the datasheet) But when I use a buck converter with a resistive load I can not achieve the left part of the IV curve. I am changing the duty cycle from 0 to 0.98 continuously (kind of) in 0.12s. I cant get the left part and I think this is logical because with a resistor at the output load there is no way that voltage will increase but current stay constant because resistor is a passive load. As in the figure below I added the figures in the folder "MPPT Resistive Load" Why I cant go to the left part of the IV curve ?

I can't remember when the UniversalOpamps first came into being, but there's a good chance there's been a bug in them from the start. Although I realised there was a problem long ago when I modified my copy of the old combined library file of UniversalOpamp2 to fix it, I had since forgotten about it. I failed to flag it up. However, when dealing with a query on another channel, I came across a significant shortfall in expected performance when using the latest stand-alone UniversalOpamp models. I was attempting to emulate the TI OPA2211 opamp with one. The datasheet for the OPA2211 states that the differential input resistance is typically 20kΩ, and the common mode input impedance is 2MΩ. Usually, the CM impedance makes little difference to the performance of most circuits because it is typically very high, so I was surprised when putting Rin=20k that the amplifier lost about 5dB of expected closed loop gain when the source impedance was significant, by comparison. I set up an impedance testjig for the UniversalOpamp3a that measured the input impedance in both modes. TL;DR: neither the differential or common mode input impedance was 20kΩ! The differential input resistance was 40kΩ, while the common mode input resistance was 10kΩ. WRONG ANSWERS! I've uploaded the test schematic: UniversalOpamp_bug1.zip The reason this happens is obvious when you look at the .subckt for UniversalOpamp3a: .subckt level3a 1 2 3 4 5 S1 5 3 N002 5 Q S2 4 5 5 N002 Q A1 2 1 0 0 0 0 N004 0 OTA G={Avol/Rout} ref={Vos} Iout={slew*Cout} Cout={Cout} en={en} enk={enk} in={in} ink={ink} Vhigh=1e308 Vlow=-1e308 C3 5 4 1p C4 3 5 1p R3 3 2 {2*Rin} noiseless G1 0 N002 N004 0 {1/Rout} R2 N002 0 {Rout} noiseless C1 N002 0 {X*Cout/Avol} R4 3 1 {2*Rin} noiseless R5 1 4 {2*Rin} noiseless R6 2 4 {2*Rin} noiseless G2 0 N004 4 N004 table(0 0 10 {2*slew*Cout}) G3 N004 0 N004 3 table(0 0 10 {2*slew*Cout}) R9 3 N004 {2*Rout} noiseless R10 N004 4 {2*Rout} noiseless .param Rout=100Meg .param Cout={Avol/GBW/2/pi/Rout} .model Q SW(Ron=10 Roff=10Meg Vt=0 Vh=-.1 Vser={Rail} ilimit={Ilimit} noiseless) .param X table(phimargin,29.4,3.5,32.1,2.9,33.8,2.6,35.8,2.3,38.1,2,40.9,1.7,43.2,1.5,45.9,1.3,49.2,1.1,53.2,0.9,58.2,0.7,64.7,0.5,73,0.3,86.1,0.05) .param Avol=1Meg GBW=10Meg Slew=10Meg rail=0 Vos=0 ilimit=25m .param en=0 enk=0 in=0 ink=0 phimargin=45 Rin=500Meg .ends level3a Resistors R3-R6 implement the supposed input resistance. Essentially, both opamp inputs have resistors of 2*Rin connected to both supply rails, and by implication (with ideal voltage sources) - to ground. Therefore each input has a resistance of Rin to ground. But - and this is a big but: Rincm = (2*Rin//2*Rin)//(2*Rin//2*Rin) = 10kΩ Rindm = (2*Rin//2*Rin)+(2*Rin//2*Rin) = 40kΩ Since the default for the Rin parameter is 500kΩ, the issues this typically causes are small compared to other parameters with typical feedback network impedances. But with the Rin parameter set to match the desire differential input impedance commonly found on datasheets of (bipolar) low noise opamps, things can go awry with those same feedback components. This should be fixed. For practical components, the common mode I/P impedance is always higher than the differential I/P impedance. So, I'd say this was a bug. -- Regards, Tony

Hi, I tried to access LTspice Help Menu this morning to check the syntax of a Directive, but found that Help on the top bar of LTspice (left clicking on LTspice Menu) opens a Notepad file with the first lines as follows .... <?xml version="1.0" encoding="utf-8" ?> <!DOCTYPE html> I'm sure this used to open a web page to the LTspice Menu. Is this a LTspice change or have I stuffed up some settings in my PC eg default settings?? I have dug around in App settings for Notepad .txt files but to no avail ... and my computer knowledge ends there. I am running Windows 11 (updated) and LTspice 24.0.12 At least I am trying to read the Help Menu .... :) :) , Ian

A dc-dc converter which has to supply an output voltage of 5 V with the output power from 2.5 W to 25 W. The variation of the output voltage of ±5% is acceptable, however, the high frequency ripple resulting from the switching process has to be limited to ±1% in order to control the noise problems. The converter is to operate from various dc sources within a range of 9 V to 16 V. You can assume that apart from the amplitude variation the input source is an ideal voltage source. The isolation is not required for this converter. The design includes a control system. The output voltage should be used for full feedback control. The only energy source in the system is the input source, therefore the power for the supply of the control block needs also to be drawn from the input source. As the power dissipation of the control block is very small compared with the load power, you can use a simple voltage regulator for this power supply. We can use the following components to design in LT spice using NE555 Resistors, including variable resistors, Capacitors, Inductors, Diodes, Zener diodes, Bipolar transistors, NE555 precision timer

I have uploaded 2 files to the temp section that model a 120 degree PTC thermistor, (the Epcos B59008C0120A040 from: http://www.epcos.com/inf/55/db/ptc_03/01770179.pdf ) including the nonlinear behavior, modeled as 4 different temperature coefficient resistors in series parallel. The model is in file PTC1.asc and the symbol is PTC_resistor.asy The model also includes the internal temperature rise and thermal time constant (which I guessed at, for lack of hard data). The symbol I created for it has a third node that produces a voltage that represents the internal temperature, with 1 volt = 1 degree C. The curve across the resistor symbol indicates the 4 slopes in the model. Everything I see this model doing looks pretty reasonable, but I would appreciate anyone going over the whole thing and making suggestions for improving it. This was my first foray into model building with Spice.

Hi All, In the uploaded file test.asc, I’m having a problem with a simulation getting stuck. Would appreciate a look. Thanks, Chris