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The simulation of the LTspice is blocked with sentence (if)

 

Hi, friends.
I have a question, have a problem with the simulation about the sentence (if).

I want to simulate a power supply with the statement (if) using the generator (bv.asy), and with the following condition :

V=if(V(Vsense)>1.2,1,0)??

I have also tried with this :

V ={si(V(Vsense)>1.2,1,0)}

The simulation do not work, is blocked,?It does not perform the transient analysis.?

I would like to know the reason of the not simulation.
You? know?the reasons why the simulation? does not work ?
AHh,?that generator is connected to the non-inverting input of the LTC6752 comparator.

I wait can to have a good help, because for me, this simulation is very important, is for a innovative electronic design .

Sorry by my bad level english.
 

Hello,

A standard V-source in SPICE cannot be a behavioral source.
You have to use a Bv-source. Add a "bv" and change V=F(...) to the formula below.

V=if(V(Vsense)>1.2,1,0)

Best regards,
Helmut
 

j.bernabe1 wrote:

? ? "I want to simulate a power supply with the statement (if) using the generator (bv.asy), and with the following condition :
? ? ?V=if(V(Vsense)>1.2,1,0)??
? ? ?...
? ? ?The simulation do not work, is blocked,?It does not perform the transient analysis."

I tried it, and it worked.? So, I guess you made a mistake.? Helmut's reply was correct, but I think you already did that.

You also tried this:
? ? "V ={si(V(Vsense)>1.2,1,0)}"
but that does not work because "si" is not a valid function name in LTspice.? It must be "if".

? ? "I would like to know the reason of the not simulation.
? ? ?You? know?the reasons why the simulation? does not work ?"

None of us can say, because (1) we don't know what the error message was, and (2) we can't see your schematic.? The error message probably was not "blocked"; it probably was something else, and it said what was wrong.

Please consider uploading your schematic to the "Temp" folder.? Also, please be more helpful by telling us the actual error message.

Regards,
Andy
 

Ok, I just to upload my schematic a (temp) folder , is a power supply .
You can see my (bv.asy) with his conditional sentence (if).
When I put to simulate the Ltspice does not begin the simulation, I seem that stalled.
 

Hello,

Every flipflop(RS, DFLOP) needs some delay either done with td and/or trise.

Right-mouse-click on the RS-flipflop.
SpiceLine: td=10n

Now it works.

Best regards,
Helmut
 

Hello,

I forgot to mention that I have uploaded a modified version of your circuit with this modification of the SR-flipflop.
SpiceLine: td=10n

Simulacion_Fuente_COG

Best regards,
Helmut
 

O.K,?thanks for your answer.?I am going? put it in practise.

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