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As part of my studies, I have to simulate a single-phase modular multilevel converter MMC (3-level) on Ltspice. I have already connected the circuit with two voltage sources of 20V each, two submodules (one upper and one lower). In the simulation I work with sine PWM, for this I have also used two carrier signals. The output voltage should be a stepped voltage between +20V and -20V and after the LC filter should be a clean sinusoidal voltage. But somehow I am not getting the desired results. (clean signals). Can someone help me. Thank you.?

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On Tue, May 6, 2025 at 03:53 PM, <Bouzid.wis@...> wrote:

Ich habe die ltspice-Datei unter dem Namen M2C single-phase SPWM112 auf Temp hochgeladen?

Remember to use English only in this group.

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Translation:? "I have uploaded the ltspice file under the name M2C single-phase SPWM112 to Temp"

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Note:? The actual filename is "M2C single phase SPWM112.asc".

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Andy

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I don't know if this matters in your simulation, but you have started with much less than a sine wave.? 9 ms is less than one-half cycle of 50 Hz.? The output waveform does not seem right, however.

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Be careful about using multiple net names on the same net.? In SPICE, every net can have only one net name ("Label" in LTspice).? One of your nets has at least three names assigned to it.? Most of the time LTspice figures it out, but sometimes it does not.

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Andy

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Bouzid.wis,

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I am having trouble trying to understand how this circuit works.

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In the upper submodule, it seems like M1 can not do much, because C1 would charge and then not pass any more current, so that closing M1 does not add any more change.? But I think it is not as simple as that.? There are multiple current paths here, including through the capacitors and through the diodes that bypass the FETs.

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Can you describe how each submodule was supposed to pull the output either up, or down?

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Is there a minimum frequency limit for the sinusoidal signal you want to synthesize?

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As drawn here, the two submodules are not symmetrical to each other.? But maybe that was just a personal choice about how the schematic was made.

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I am only guessing here, but it looks like maybe you have one of the submodules inverted.? When the voltage V(ControlA) approaches +1V, the FETs with the DC path (M2 and M4) are both OFF while the two with series capacitors and no DC path (M1 and M3) are both ON.? So very little current can flow through L2 or L3, to or from the load.? When V(ControlA) approaches -1V, it is the opposite:? both DC-path FETS are ON, resulting in lots of current in L2 and then out L3 without making it to the output load.? In both cases, the output gets nothing.? Check your connections because I think it is not right.

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But as far as SPICE goes, I think it simulates OK.

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FYI, there are easier ways to generate triangle waves.? The normal voltage source with PULSE is ideal for this.

? ? Vm Tri_up 0 PULSE (-1 1 0 50u 50u 0 100u)

? ? Vn Tri_dwn 0 PULSE (1 -1 0 50u 50u 0 100u)

or

? ? .param RF=0.5/fs? ; Rise and Fall time

? ? Vm Tri_up 0 PULSE (-1 1 0 {RF} {RF} 0 {2*RF})

Andy

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Bouzid.wis,

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See this schematic I uploaded:

in the Temp folder.

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I swapped (interchanged) two of the signals.? Now it seems to work.? That confirms my suspicion that one of your sections was inverted or backwards.

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Andy

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I have uploaded the picture in the photo under the album MMC single phase.

On Fri, May 9, 2025 at 05:43 PM, <Bouzid.wis@...> wrote:

Upper submodule: When the upper MOSFETs (e.g. S1) are conducting, the positive voltage of the upper capacitor is applied to the output, while the lower MOSFETs (e.g. S2) close the current path or bypass the upper branch.

I am sorry, but that description does not explain to me how it works, not in a way I can understand.? There are many things interacting here, including the fact that the source of pull-up current is through a resistor and an inductor, it is not a voltage source, and there is a capacitor in the current path when M1 switches ON.? Plus there is the reactive input impedance of the output filter.? M1 does not directly switch a positive voltage to the unfiltered output, which I think was what you think would happen.? For that to happen, R1 and L2 and C1 should not be there.

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Do you understand how it is really supposed to work?

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the two submodules must be symmetrical to each other, can you show me where the problem is.

What is the problem?? Is there a problem?

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Are the two submodules not symmetrical to each other?

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I see a sine wave at the filtered output, and it looks like a reasonable replica of the input sine wave.? That suggests that maybe the circuit works.

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yes I have looked at the file, but the output voltage should not look like this.

please have a look at the picture i uploaded in the temp named output.

I think you are mistaken if you think the unfiltered output should alternate between +20 V, 0 V, and -20 V.? I do not see a way for your first circuit to make the unfiltered voltage do that.

i also uploaded another simulation circuit (named M2C single phase SPWM11) where i simulated the circuit with only one carrier signal, but the unfiltered voltage is not stepped with clear voltage levels: +20V, 0V, -20V, but only +20V, -20V. Probably because I only used one carrier signal. But the current at the load and the filtered voltage look good.

How would the unfiltered output voltage go to 0 V?? Is there anything in your circuit that can drive the unfiltered output to 0 V?? I do not see one.

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But I hope you realize I am unfamiliar with this circuit, and that does not help me explain what happens or does not happen.? I am "in the blind".

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Andy

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