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Howdy

I am tying myself in knots trying to examine the buildup of phase in a relatively simple regulator circuit. ?I have uploaded Phase Analysis.zip to the files section. File darlington.asc contains two schematics, the second of which has been set up to examine phase and gain margin by breaking the feedback loop and inject AC small signal of 1. Run the simulation and plot -V(Vout_DD_stab)/V(Y) provides loop gain and phase. ?I read phase margin as the absolute difference between the reading for phase at the UGF and 0 or 180/-180 whichever is closer. ?In this case, I read -91 degrees for phase at UGF of 1.35Mhz and hence understand my phase margin is 89 degrees. (I understand that the -180 degree phase shift from the op amp inversion is omitted, presumably for simplicity.)

[Incidentally, a few days ago LTspice produced the plot in Phase and Gain Margin - old.jpg. Note the differences in gain below about 10kHz. That plot was produced in an earlier schematic. I later encountered problems with the schematic no longer recognising .inc statements and hence refusing to work. I therefore produced a new schematic from scratch but updated LTspice at the same time. I've examined every inch of the schematic and there are no differences that I can see from old to new (all components and values are the same) and yet, while the UGF and phase margin results are the same, the gain plot below 10kHz is significantly different and seemingly 'less correct.' At this stage I can only (very gingerly) conclude that this resulted from the update to LTspice. ?Eek...]

I now want to understand the contributors to the additional 91 degrees of phase shift and I am unsure of how best to probe the schematic when the loop is broken in this fashion. I have plotted several other traces.

A. ?-V(vout_dd_stab)/V(OA_Out2) is intended to look at the phase shift from feedback network through to the output of the op amp. (Perhaps I have to change the numerator and denominator to see a plot of -180 degrees.) In a perfect world I would expect to see a flat line at 180 degrees. ?

B. ?-V(vout_dd_stab)/V(Shift_Out2) is intended to add in the level shift network. As I would expect, judging from the lack of difference between this and the trace discussed above, the level shift is not contributing to phase shift.?

C. ?-V(vout_dd_stab)/V(Driver_Out2) is intended to add in the driver transistor EF. Given the very limited difference between this trace and those above I conclude there is little contribution to phase shift from the driver transistor.?

D. ?Presumably one would ordinarily conclude the balance of the (modelled) phase shift it coming from the pass transistor.?

Am I 'probing' the schematic in correct fashion? Is there an easier way? I don't seem to be able to use a differential probe to identify phase shift between two points. For example, it would seem 'natural'?(on a Mac)?to be able to place the probe on Shift_Out2, left-click and hold while dragging it to OA_Out2 before releasing in order to examine any phase shift from the level shift network. ?Doing so, however, does not produce a flat phase line at 0 which one would conclude from examining the (lack of difference between) the first two traces discussed above (A and B). How can I directly plot the phase shift contribution of the pass transistor to test D above? ?Ordinarily I would not have thought it would contribute any significant phase shift.?

Thanks in advance for any assistance

Steve

#90183

Steve wrote a rather lengthy message, including:

? ?"I read phase margin as the absolute difference between the reading for phase at the UGF and 0 or 180/-180 whichever is closer."

It can't be either/or.? It must be only one of them, depending on how you have kept track of polarities.? Phase margin can be >90 degrees, so it's not the one that is closer (which forces it to be <90 degrees).

The fact that you added a minus sign to the thing being plotted, adds -180 degrees to the phase plot.

? ?"[Incidentally, a few days ago LTspice produced the plot in Phase and Gain Margin - old.jpg. ...

? ? At this stage I can only (very gingerly) conclude that this resulted from the update to LTspice.? Eek...]"

It's very unlikely.

There probably was a difference between your circuits.? But they can be hard to find.? Sometimes, comparing the .net files makes it easier to find their differences.

One problem with visually comparing schematics, is that attributes can be made not visible.

? ?"...?problems with the schematic no longer recognising .inc statements ..."

That should not have happened either, and points to something being wrong in the schematic, or with the included files themselves.? Typo?

Sorry, your questions are very complicated and it's late.? I'll try to write more later.

Andy

Steve Kale

#90191

开云体育

On 9 Aug 2016, at 07:17, Andy wrote:

It can't be either/or.? It must be only one of them, depending on how you have kept track of polarities.? Phase margin can be >90 degrees, so it's not the one that is closer (which forces it to be <90 degrees).

The fact that you added a minus sign to the thing being plotted, adds -180 degrees to the phase plot.

Duh. ?The first point makes sense. ?I’ve clearly been getting confused between the graph portraying phase (excluding the op amp's 180 degrees) and phase margin directly. Plus the impact of the minus sign. ?Of course, in the example I posted, if it is not applied then the graph would read +89 degrees. If it is then the graph reads -91 degrees. It seems odd to talk about a negative margin but Helmut had some time ago told me to plot with the minus sign.

??

? ?"[Incidentally, a few days ago LTspice produced the plot in Phase and Gain Margin - old.jpg. ...
? ? At this stage I can only (very gingerly) conclude that this resulted from the update to LTspice.? Eek...]"

It's very unlikely.

There probably was a difference between your circuits.? But they can be hard to find.? Sometimes, comparing the .net files makes it easier to find their differences.

One problem with visually comparing schematics, is that attributes can be made not visible.

? ?"...?problems with the schematic no longer recognising .inc statements ..."

That should not have happened either, and points to something being wrong in the schematic, or with the included files themselves.? Typo?

I have poured over the two schematics including all value/spice line statements (CTRL-left click on a device) and can see no differences. ?I can’t run the old schematic at the moment as I’m currently getting an error “missing model definition for QD44VH10” even though I clearly have the .inc statement for the model file (I have even deleted the Spice directive - it’s not a comment - and added it again) and CTRL-left click on every QD44VH10 device reveals exactly the same as the new file I posted. (Both .asc files sit in the same folder and so both have access to the same model text file.) I will go back to it at some point (and may even check older versions via Mac’s Time Machine facility) as I do want to see if the sub 1k behaviour remains the same. ?However, for now I have just moved on as I am most focused on how to appropriately probe the circuit for the loss of phase margin. I want to understand how each piece of the circuit degrade phase margin beyond the 180 degrees from the op amp. ?Of course, when I don’t have confidence I am using LTspice properly in this regard it becomes rather hard to have confidence in the results.?

Sorry, your questions are very complicated and it's late.? I'll try to write more later.

Andy

I very much appreciate it Andy.

I’m also focused on ‘disconnects’** between the two forms of analysis: ?top circuit AC injection at Vin and modelling Vout vs freq for line rejection and bottom circuit loop gain and phase analysis. ?If, for example, I make a change to the output caps in the bottom circuit such that UGF is extended (output cap pole or zero is affected) and/or greater loop gain is applied I would expect the identical change in the top circuit to extend the line rejection in similar fashion (greater feedback being applied or being applied to higher frequencies). ?Yet it doesn’t.?

** disconnects that may well be just my lack of knowledge

regards

Steve

Steve Kale

#90193

开云体育

Actually I just now found the problem with the missing model definition statement although I don’t understand why it is one. ?In my older schematic I had, at one stage, wanted to test the impact of a different pass transistor and rather than use a .inc statement for this new transistor’s subcircuit statement I had pasted it directly into the circuit (see below). ?If I make it a comment, I no longer get the error message in relation to the missing model statement for Qd44vh10. ?If I make it a Spice directive I do - even though I am not using the subcircuit at all in the sim and the error doesn’t relate to the 2sc6144sg at all. ?

???

Now, the sub 1kHz behaviour remains the same as the image I had uploaded in the zip file (i.e. different from my new circuit) so I need to track down what’s causing that difference.

2SC6144SG SPICE PARAMETER ***

* DATE : 2015/03/13 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??

* Temp = 27 deg

.SUBCKT 2SC6144SG 1 2 3

Q1 1 2 3 ?C6144SG ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??

? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??

.MODEL C6144SG npn ( ? ? ? IS ? ? ? = 3.500p ? ? ? ? BF ? ? ? = 335 ? ? ? ? ??

+NF ? ? ? = 1 ? ? ? ? ? ? ?VAF ? ? ?= 9 ? ? ? ? ? ? ?IKF ? ? ?= 13 ? ? ? ? ? ?

+ISE ? ? ?= 50.00p ? ? ? ? NE ? ? ? = 2 ? ? ? ? ? ? ?BR ? ? ? = 160 ? ? ? ? ??

+NR ? ? ? = 1 ? ? ? ? ? ? ?VAR ? ? ?= 26 ? ? ? ? ? ? IKR ? ? ?= 2.9 ? ? ? ? ??

+ISC ? ? ?= 230.0p ? ? ? ? NC ? ? ? = 2 ? ? ? ? ? ? ?RB ? ? ? = 910.0m ? ? ? ?

+IRB ? ? ?= 100.0m ? ? ? ? RBM ? ? ?= 22.20m ? ? ? ? RE ? ? ? = 20.50m ? ? ? ?

+RC ? ? ? = 3.300m ? ? ? ? XTB ? ? ?= 1.9 ? ? ? ? ? ?EG ? ? ? = 1.11 ? ? ? ? ?

+XTI ? ? ?= 3 ? ? ? ? ? ? ?CJE ? ? ?= 1.420n ? ? ? ? VJE ? ? ?= 750.0m ? ? ? ?

+MJE ? ? ?= 383.0m ? ? ? ? TF ? ? ? = 450p ? ? ? ? ? XTF ? ? ?= 7 ? ? ? ? ? ??

+VTF ? ? ?= 1.000K ? ? ? ? ITF ? ? ?= 20 ? ? ? ? ? ? PTF ? ? ?= 0 ? ? ? ? ? ??

+CJC ? ? ?= 230.0p ? ? ? ? VJC ? ? ?= 520.0m ? ? ? ? MJC ? ? ?= 418.0m ? ? ? ?

+XCJC ? ? = 1 ? ? ? ? ? ? ?TR ? ? ? = 1.000n ? ? ? ? FC ? ? ? = 500.0m ? ? ? ?

+KF ? ? ? = 0 ? ? ? ? ? ? ?AF ? ? ? = 1 ? ? ? ? ? ? ?) ? ? ? ? ? ? ? ? ? ? ? ?

* ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??

.ENDL 2SC6144SG ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??

? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??

* ?Information herein is for example only; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?

* ?it is not guaranteed for volume production. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?

? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??

* ON Semiconductor

Show quoted text

On 9 Aug 2016, at 11:11, Steve ?wrote:

I have poured over the two schematics including all value/spice line statements (CTRL-left click on a device) and can see no differences. ?I can’t run the old schematic at the moment as I’m currently getting an error “missing model definition for QD44VH10” even though I clearly have the .inc statement for the model file (I have even deleted the Spice directive - it’s not a comment - and added it again) and CTRL-left click on every QD44VH10 device reveals exactly the same as the new file I posted. (Both .asc files sit in the same folder and so both have access to the same model text file.) I will go back to it at some point (and may even check older versions via Mac’s Time Machine facility) as I do want to see if the sub 1k behaviour remains the same. ?

#90197

Hello Steve

You wrote:
" That plot was produced in an earlier schematic. I later encountered problems with the schematic no longer recognising .inc statements and hence refusing to work. "

Have you still the .log file you got when you tried to run the earlier schematic ?

Note that in
.SUBCKT 2SC6144SG 1 2 3
Q1 1 2 3? C6144SG??????????????????????????????????????????????????????????????
?????????????????????????????????????????????????????????????????????????????
.MODEL C6144SG npn (?????? IS?????? = 3.500p???????? BF?????? = 335??????????
+NF?????? = 1????????????? VAF????? = 9????????????? IKF????? = 13???????????
+ISE????? = 50.00p???????? NE?????? = 2????????????? BR?????? = 160??????????
+NR?????? = 1????????????? VAR????? = 26???????????? IKR????? = 2.9??????????
+ISC????? = 230.0p???????? NC?????? = 2????????????? RB?????? = 910.0m???????
+IRB????? = 100.0m???????? RBM????? = 22.20m???????? RE?????? = 20.50m???????
+RC?????? = 3.300m???????? XTB????? = 1.9??????????? EG?????? = 1.11?????????
+XTI????? = 3????????????? CJE????? = 1.420n???????? VJE????? = 750.0m???????
+MJE????? = 383.0m???????? TF?????? = 450p?????????? XTF????? = 7????????????
+VTF????? = 1.000K???????? ITF????? = 20???????????? PTF????? = 0????????????
+CJC????? = 230.0p???????? VJC????? = 520.0m???????? MJC????? = 418.0m???????
+XCJC???? = 1????????????? TR?????? = 1.000n???????? FC?????? = 500.0m???????
+KF?????? = 0????????????? AF?????? = 1????????????? )???????????????????????
*????????????????????????????????????????????????????????????????????????????
.ENDL 2SC6144SG

.ENDL? should be ENDS

LTspice can't run with .endl

Regards
PhB

Steve Kale

#90198

开云体育

Hi Philippe

I have pasted below the log file I get when (a) the 2SC6144SG subcircuit Spice directive is not made a comment and (b) I “OK” through the errors rather than cancelling the run.

Thanks for the correction to the .subckt. ?I got this from the On Semi website. Could this be a Spice D vs LTspice translation issue or just error?

Note I also found I had to alter their pin order in the line beginning Q1. They had:

Q1 2 1 3 ?C6144SG

But I’m not sure why this should give me the issue I encountered when the Spice directive wasn’t even being called upon…

Regards

Steve

Circuit: * /Users/steve/Desktop/Spice Modelling/Sziklai AD817A/Reg Circuits.asc

Error on line 101 : q13 n053 n062 vout-darlpp 0 qd44vh10