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.savebias command commented out
g.moberg
Hello All,
I have been trying to use the .savebias command to grab a starting point for a rather lengthy transient simulation of a Linear Tech SMPS circuit. I believe I have the correct syntax: .savebias Skip internal time=19.999ms to write the data to file "Skip", including internal nodes, at time 19.999ms. However, the file is not created, and upon examination, the SPICE Error Log shows that the .savebias command is present but is commented out. It is highlighted in red in the word file of the error log. I have tried numerous hacking such as deleting "internal", changing the time, shortening the filename, but to no avail. I have been able to use .savebias and .loadbias successfully in other circuits. I have uploaded the required files to the "Temp" folder. Unzip the archive and run the schematic file. Stop the simulation immediately (it takes a very long time), and examine the SPICE Error Log near the end of the file, and you will see the problem. I have looked in the "files" section of the Yahoo site, and read the "Help" section several times without discerning what the problem is. My only thought is that it might have something to do with the encrypted LT3958 subcircuit. I would appreciate it if anyone could shed some light on this. Thanks a lot. Incidentally, if you are composing a message, don't click to another part of the yahoo site, or you will lose your message. Greg Moberg |
--- In LTspice@..., "g.moberg" <gregory.moberg@...> wrote:
Hello Greg, I just run your simulation and got a bias point file "skip" after the simulation has reached the 19.995ms. The simulation is still running at the moment at 23ms. Best regards, Helmut |
Ganesan
You had a floating resistor Routn1.. I connected it to outn and simulated..
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I get the following skip file * .SAVEBIAS from circuit: * C:\Documents and Settings\ganesan\My Documents\Downloads\SaveBias Test\SaveBias Test\LT3958 05.asc * time=0.019995 .nodeset V(vff)=-15.87393777 V(vee)=-6.001003683 V(vcc)=17.5 V(vdd)=5 V(ps1:von)=1 + V(ramp)=1 V(ramp-)=0 V(ps1:n001)=17.5 V(ps1:n002)=5 V(ps1:n003)=-6.001065688 V(ps1:n004)=-15.89810071 + V(vrt1)=-14.68364284 V(sgnd)=-15.8739326 V(vf1)=-14.80382612 V(vsw)=-15.64559458 + V(vd)=-23.60401786 V(vc)=-14.2683469 V(p001)=-14.27289193 V(vss1)=-14.96836013 V(voutn)=-7.94231326 + V(n003)=-8.587430434 V(n002)=-7.991617608 V(vccint)=-6.147890685 V(u1:n018)=-15.47457076 + V(u1:n016)=-15.83406013 V(u1:n015)=-14.8739326 V(u1:n019)=-15.15819998 V(u1:n021)=-15.8739326 + V(u1:n017)=-14.93106454 V(u1:n020)=-6.147711599 V(u1:n027)=-14.80381024 V(u1:n003)=-14.8739326 + V(vs)=-15.83386799 V(u1:n007)=-14.8739326 V(u1:n001)=-14.8739326 V(u1:n004)=-8.123932601 + V(u1:n009)=0.0967940426 V(n001)=-13.9644065 V(u1:n006)=-14.8739326 V(u1:n005)=-14.8739326 + V(u1:n024)=-15.8739326 V(u1:n026)=-15.8739326 V(u1:n014)=-14.66120599 V(u1:n023)=-14.6739326 + V(u1:n013)=-14.66909605 V(u1:n025)=-16.94407367 I(l1b)=1.857359465 I(l1a)=1.110787936 Where is the beef? Cheers AG On 9/14/2011 1:59 PM, g.moberg wrote:
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--- In LTspice@..., "g.moberg" <gregory.moberg@...> wrote:
Greg, I couldn't dupicate your problem. I did change the .savebias time to 1msec and added internal to it, and it worked fie. Note that the name of the file will be Skip with no extension. Rick |
g.moberg
Hello Rick and All,
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Well, it seems to be operating properly now, in that the "Skip" file shows up, though the .savebias command is still commented out in the log file. I spent several hours yesterday trying to make this work without success. Thanks for looking at this - y'all must have scared it. Greg --- In LTspice@..., "Rick" <sawreyrw@...> wrote:
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g.moberg
Hello Again,
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Just to finish this topic out, today I generated the "Skip" file successfully. Since this is an SMPS circuit whose inductor currents are not zero, I edited the "Skip" file to change its .nodeset command to a .ic command, and set the initial conditions of the 2 inductors to their approximate values at the time the .savebias command executed. This changes the inductor characteristics for initial convergence from short circuits to ideal current sources with the specified initial conditions. This must be done to prevent the circuit from converging to a highly erroneous state with 0V across the inductors. The simulation picked up very close to where I expected it to, and settled quickly so I can do the load transient analysis without waiting minutes to get to a settled condition. Thanks again for those who looked at this. Greg Moberg --- In LTspice@..., "g.moberg" <gregory.moberg@...> wrote:
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