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After a few years, I came to ngspice and did some test to look better at strange behavior seen on LTspice .TRAN analysis for a simple circuit involving a current source across an inductor. Namely: ?
I1 0 v1 10
L1 v1 0 10u IC=10 Rser=1m
.tran 10n 1m uic
.ic V(v1)=0
.backanno
.end
?
LTspice returns a spike of 20kA for the I(L1) current at timestamp t=0. I realized that ngspice for .TRAN UIC analysis does not include in the analysis's output such t=0 timestamp at all. Btw, one can check the MNA linear system it solves at each step and indeed there is no such system defined at t=0. The index 0 element of any .TRAN UIC analysis's output vector just refers to the first timestamp after t=0.
?
I did another try with ngspice by changing the .ic directive to .ic V(v1)=-15. Exact the same result: as expected the .ic initial condition on v1 node voltage does not affect the solution at all since there is no capacitor across that node and GND.
?
I believe LTspice .TRAN UIC analysis's output at t=0 timestamp is actually garbage. Maybe Mike had a good reason for that, however I hope ADI will fix it in future releases.
?
Ps: to get rid of this one can use the .options Thev_induc=1 directive forcing LTspice to employ the Thevenin equivalent for the finite-difference time-integration method used (e.g. Backward-Euler).
?
Carlo.
?
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On Mon, Feb 24, 2025 at 06:38 AM, Carlo wrote:
I1 0 v1 10
L1 v1 0 10u IC=10 Rser=1m
.tran 10n 1m uic
.ic V(v1)=0
.backanno
.end
Note that you neglected to include the Title line or command.? The first line of any SPICE Netlist that is suitable for running, is always ignored.
?
You can copy-and-paste this netlist into a schematic.? But it should not be run by itself in batch mode, or results could be meaningless.
?
I think you should stop quibbling about transient behavior when UIC is specified.? You may never get agreement between different SPICE programs about this, and you may not even get what seems to you to be sensible behavior from a nonsense simulation.? Be aware that LTspice's construct with an inductor having non-zero series resistance Rser, is a special implementation that did not exist in traditional SPICE.? I do not know (at least at this moment) how it is constructed internally and exactly what makes it behave the way that it does.? For all I know, it might be a Nortonized equivalent circuit, not a Thevenin (L+R in series), which would be consistent with the fact that the L+Rser does not add a node to the netlist.? "LTspice uses proprietary circuit simulation technology to simulate this physical inductor without any internal nodes."
?
You seem to be very intent on trying to prove the behavior incorrect.? Please stop trying to do that.? You will only drive yourself (and us) crazy.
?
Whenever UIC is used, results might appear to be incorrect.? Internal to LTspice, they are not.? FYI, this has been argued over 23 years of this group's existence.
I believe LTspice .TRAN UIC analysis's output at t=0 timestamp is actually garbage. Maybe Mike had a good reason for that, however I hope ADI will fix it in future releases.
I am sure it is not garbage, and it should not be changed.? But its understanding may be clouded and mysterious.
?
Andy
?
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On the face of it, setting IC of L1 = 10, but
also specifying UIC is paradoxical. I suppose IC = 10 doesn't
count as an 'initial condition' despite the name. Evidence of
this is the huge voltage spike at t = 0, which presumably is the
way that the 10 A current is produced instantaneously.
On 2025-02-24 13:46, Andy I via
groups.io wrote:
On Mon, Feb 24, 2025 at 06:38 AM, Carlo wrote:
I1 0 v1 10
L1 v1 0 10u IC=10 Rser=1m
.tran 10n 1m uic
.ic V(v1)=0
.backanno
.end
Note that you neglected to include the Title line or command.?
The first line of any SPICE Netlist that is suitable for
running, is always ignored.
?
You can copy-and-paste this netlist into a schematic.? But it
should not be run by itself in batch mode, or results could be
meaningless.
?
I think you should stop quibbling about transient behavior
when UIC is specified.? You may never get agreement between
different SPICE programs about this, and you may not even get
what seems to you
to be sensible behavior from a nonsense simulation.? Be aware
that LTspice's construct with an inductor having non-zero series
resistance Rser, is a special implementation that did not exist
in traditional SPICE.? I do not know (at least at this moment)
how it is constructed internally and exactly what makes it
behave the way that it does.? For all I know, it might be a
Nortonized equivalent circuit, not a Thevenin (L+R in series),
which would be consistent with the fact that the L+Rser does not
add a node to the netlist.? "LTspice
uses proprietary circuit simulation technology to simulate
this physical inductor without any internal nodes."
?
You seem to be very intent on trying to prove the behavior
incorrect.? Please stop trying to do that.? You will only drive
yourself (and us) crazy.
?
Whenever UIC is used, results might appear to be incorrect.?
Internal to LTspice, they are not.? FYI, this has been argued
over 23 years of this group's existence.
I believe LTspice .TRAN UIC analysis's output at t=0
timestamp is actually garbage. Maybe Mike had a good reason
for that, however I hope ADI will fix it in future releases.
I am sure it is not garbage, and it should not be changed.? But
its understanding may be clouded and mysterious.
?
Andy
?
--
OOO - Own Opinions only
If something is true:
* as far as we know - it's science
*for certain - it's mathematics
*unquestionably - it's religion
|
On Mon, Feb 24, 2025 at 05:46 AM, Andy I wrote:
Note that you neglected to include the Title line or command.? The first line of any SPICE Netlist that is suitable for running, is always ignored.?You can copy-and-paste this netlist into a schematic.? But it should not be run by itself in batch mode, or results could be meaningless.
Ah ok, got it.
?
Be aware that LTspice's construct with an inductor having non-zero series resistance Rser, is a special implementation that did not exist in traditional SPICE.? I do not know (at least at this moment) how it is constructed internally and exactly what makes it behave the way that it does.? For all I know, it might be a Nortonized equivalent circuit, not a Thevenin (L+R in series), which would be consistent with the fact that the L+Rser does not add a node to the netlist.? "LTspice uses proprietary circuit simulation technology to simulate this physical inductor without any internal nodes."
Yes, I'm aware of it. With a non-zero inductor's Rser, the special implementation employs a Nortonized equivalent circuit in order to reduce the MNA system's matrix size (the inductor's current is no longer an unknown of the linear system).
?
Carlo.
?
?
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On Mon, Feb 24, 2025 at 06:11 AM, John Woodgate wrote:
On the face of it, setting IC of L1 = 10, but also specifying UIC is paradoxical. I suppose IC = 10 doesn't count as an 'initial condition' despite the name. Evidence of this is the huge voltage spike at t = 0, which presumably is the way that the 10 A current is produced instantaneously.
No, IC=10 at inductor component level does count as inductor's current initial condition for .TRAN UIC analysis. Indeed the v1 voltage spike at 2nd datapoint (not at the first) changes according that IC= initial condition. Check the result for instance changing IC=10 to IC=1.
?
It basically affects the value of the derivative di/dt at the 2nd datapoint.
?
Carlo.
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On Mon, Feb 24, 2025 at 09:11 AM, John Woodgate wrote:
On the face of it, setting IC of L1 = 10, but also specifying UIC is paradoxical.
That is actually normal for SPICE syntax.? Specifying UIC tells SPICE to definitely use that IC setting.? No paradox.
?
There may be some difference in the details, between how different SPICE programs handle it.? But I think it is basically like this:? Specifying initial conditions (either IC= or .IC) works differently depending on whether UIC is also used.? Without UIC, SPICE applies the initial conditions, lets the circuit converge, then it might remove the enforcing conditions and lets it converge again.? Therefore, whether or not it does the second step, it starts with a self-consistent set of voltages and currents.? Whereas, when you add UIC, SPICE omits trying to converge.? It just accepts the initial conditions you specify (including 0 for any not specified), and accepts them as is.? ?No attempt to solve the network equations with those conditions.? Therefore it is almost guaranteed to "burp" when the transient simulation begins.? You got what you asked for, even if it is garbage.
?
I can't guarantee that what I described above happens in all SPICE programs, but this was my understanding, from decades ago.
?
I suppose IC = 10 doesn't count as an 'initial condition' despite the name.
It does count as an "initial condition".? But it needs to be taken with care.
?
?
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On Mon, Feb 24, 2025 at 06:30 AM, Andy I wrote:
Specifying initial conditions (either IC= or .IC) works differently depending on whether UIC is also used.? Without UIC, SPICE applies the initial conditions, lets the circuit converge, then it might remove the enforcing conditions and lets it converge again.? Therefore, whether or not it does the second step, it starts with a self-consistent set of voltages and currents.? Whereas, when you add UIC, SPICE omits trying to converge.? It just accepts the initial conditions you specify (including 0 for any not specified), and accepts them as is.? ?No attempt to solve the network equations with those conditions.
Sorry, without UIC LTspice lets the circuit converge (i.e. basically it works out the DC Initial Transient Solution/ITS including the voltages/charges and currents/fluxes for capacitors and inductors respectively to use as their actual initial conditions to start the transient from). What do you mean by
... then it might remove the enforcing conditions and lets it converge again
? Thanks.
?
?
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On Mon, Feb 24, 2025 at 09:49 AM, Carlo wrote:
What do you mean by
... then it might remove the enforcing conditions and lets it converge again
I mean that it might remove the IC= or .IC enforced conditions, and run another pass looking for convergence.
?
Whether or not it does that, is not the point I was making.? The point is that it begins the transient analysis by starting at a consistent operating point where convergence was reached.
?
Andy
?
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Yes, that was my conclusion.
On 2025-02-24 14:29, Carlo wrote:
On Mon, Feb 24, 2025 at 06:11 AM, John Woodgate wrote:
On the face of it, setting IC of L1 = 10, but also
specifying UIC is paradoxical. I suppose IC = 10 doesn't count
as an 'initial condition' despite the name. Evidence of this
is the huge voltage spike at t = 0, which presumably is the
way that the 10 A current is produced instantaneously.
No, IC=10 at inductor component level does count as
inductor's current initial condition for .TRAN UIC analysis.
Indeed the v1 voltage spike at 2nd datapoint (not at the first)
changes according that IC= initial condition. Check the result
for instance changing IC=10 to IC=1.
?
It basically affects the value of the derivative di/dt at the
2nd datapoint.
?
Carlo.
--
OOO - Own Opinions only
If something is true:
* as far as we know - it's science
*for certain - it's mathematics
*unquestionably - it's religion
|
I think it does look like a paradox. It one
were doing a Laplace analysis with pencil and paper, I(L1)? = 10
A would definitely be an 'initial condition'. But I did conclude
that it isn't in LTspice.
On 2025-02-24 14:30, Andy I via
groups.io wrote:
On Mon, Feb 24, 2025 at 09:11 AM, John Woodgate wrote:
On the face of it,
setting IC of L1 = 10, but also specifying UIC is
paradoxical.
That is actually normal for SPICE syntax.? Specifying UIC
tells SPICE to definitely use that IC setting.? No paradox.
?
There may be some difference in the details, between how
different SPICE programs handle it.? But I think it is basically
like this:? Specifying initial conditions (either IC= or .IC)
works differently depending on whether UIC is also used.?
Without UIC, SPICE applies the initial conditions, lets the
circuit converge, then it might remove the enforcing conditions
and lets it converge again.? Therefore, whether or not it does
the second step, it starts with a self-consistent set of
voltages and currents.? Whereas, when you add UIC, SPICE omits
trying to converge.? It just accepts the initial conditions you
specify (including 0 for any not specified), and accepts them as
is.? ?No attempt to solve the network equations with those
conditions.? Therefore it is almost guaranteed to "burp" when
the transient simulation begins.? You got what you asked for,
even if it is garbage.
?
I can't guarantee that what I described above happens in all
SPICE programs, but this was my understanding, from decades ago.
?
I suppose IC = 10 doesn't
count as an 'initial condition' despite the name.
It does count as an "initial condition".? But it needs to be
taken with care.
?
?
--
OOO - Own Opinions only
If something is true:
* as far as we know - it's science
*for certain - it's mathematics
*unquestionably - it's religion
|
On Mon, Feb 24, 2025 at 12:15 PM, Carlo wrote:
Do you mean it might try to compute another/different ITS pass ...
You appear to be extremely insistent by asking this question over and over, as if asking it every few minutes will twist my arm and force me to answer you immediately.
?
I don't work that way.
?
Go somewhere else.? Take your nagging to another forum.? Keep it up, and you'll be permanently out of here.
?
Andy
?
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Apologize, I just wanted to make sure I understood it correctly :-)
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Carlo
John Woodgate