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I agree, of course, but the AD797 is a (costly) opamp. It should not produce a TSTS error in that .ASC. Without a lot of digging, it isn't possible to confirm that it is connected correctly; for example, is node 38 really the output? The .ASC appears to work with the simple opamp.. It could hardly refuse.

On Mon, Feb 24, 2025 at 09:03 AM, john23 wrote:

Hello ,I have the following file which is presenting an error shown below

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Convergence Failure: ?Time step too small; time = 8.11724e-08, timestep = 1.25e-19: trouble with instance "u1:DSC1"

I assume this is the failure you asked about.

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"Time step too small" errors are unfortunately difficult to deal with.? If this is your first time encountering a "timestep too small" error, "welcome to the club".

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"Time step too small" errors happen for this reason.? When SPICE can't converge at any timepoint, it backs up to the previous one, sets the time step smaller (I think by a factor of 8), and tries again.? It is more likely to find convergence by not trying to go too far into the future, so a smaller timestep after the last good point is more likely to solve, and then it can move on.

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But occasionally that doesn't work.? It keeps trying smaller and smaller timesteps, until eventually the timestep gets ridiculously small, and SPICE/LTspice aborts with that error message.

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The root problem is most likely because there is something in the circuit that behaves badly.? Maybe a component's function or its derivative has a discontinuity.? Both are bad for SPICE and should never happen, but many models have discontinuities and can lead to these problems.? The best remedy is to fix the models.? But often we can't do that.? There are a handful of other things that can sometimes help,?

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Download the FAQ file.? Open it and read until you find the section about "time step too small" errors, and start reading.? There are a couple dozen suggestions that MIGHT help.? There is no guarantee that you can ever fix a "time step too small" error.

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When I ran your simulation, I do not (yet) have a "time step too small" error, but it has not found the initial DC solution yet.? Time step too small errors can happen even during the initial DC solution phase, because one of the algorithms is "Pseudo-Tran", which applies the transient solver to finding the DC solution.? Sometimes it can abort in that phase, even though it is not a .TRAN simulation at all.

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Andy

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I think it does look like a paradox. It one were doing a Laplace analysis with pencil and paper, I(L1)? = 10 A would definitely be an 'initial condition'. But I did conclude that it isn't in LTspice.

On Mon, Feb 24, 2025 at 09:11 AM, John Woodgate wrote:

On the face of it, setting IC of L1 = 10, but also specifying UIC is paradoxical.

That is actually normal for SPICE syntax.? Specifying UIC tells SPICE to definitely use that IC setting.? No paradox.

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There may be some difference in the details, between how different SPICE programs handle it.? But I think it is basically like this:? Specifying initial conditions (either IC= or .IC) works differently depending on whether UIC is also used.? Without UIC, SPICE applies the initial conditions, lets the circuit converge, then it might remove the enforcing conditions and lets it converge again.? Therefore, whether or not it does the second step, it starts with a self-consistent set of voltages and currents.? Whereas, when you add UIC, SPICE omits trying to converge.? It just accepts the initial conditions you specify (including 0 for any not specified), and accepts them as is.? ?No attempt to solve the network equations with those conditions.? Therefore it is almost guaranteed to "burp" when the transient simulation begins.? You got what you asked for, even if it is garbage.

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I can't guarantee that what I described above happens in all SPICE programs, but this was my understanding, from decades ago.

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I suppose IC = 10 doesn't count as an 'initial condition' despite the name.

It does count as an "initial condition".? But it needs to be taken with care.

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Andy

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.MEAS T1 when V(test)=0
.MEAS T2 when V(test)<>0
.MEAS T3 when V(test)>=0
.MEAS T4 when V(test)<=0
.MEAS T5 when V(test)<0
.MEAS T6 when V(test)<0

Sorry, copy-paste error. Should have been:

.MEAS T1 when V(test)=0
.MEAS T2 when V(test)<>0
.MEAS T3 when V(test)>=0
.MEAS T4 when V(test)<=0
.MEAS T5 when V(test)<0
.MEAS T6 when V(test)>0

Same result.

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Yes, that was my conclusion.

On Mon, Feb 24, 2025 at 06:11 AM, John Woodgate wrote:

On the face of it, setting IC of L1 = 10, but also specifying UIC is paradoxical. I suppose IC = 10 doesn't count as an 'initial condition' despite the name. Evidence of this is the huge voltage spike at t = 0, which presumably is the way that the 10 A current is produced instantaneously.

No, IC=10 at inductor component level does count as inductor's current initial condition for .TRAN UIC analysis. Indeed the v1 voltage spike at 2nd datapoint (not at the first) changes according that IC= initial condition. Check the result for instance changing IC=10 to IC=1.

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It basically affects the value of the derivative di/dt at the 2nd datapoint.

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Carlo.

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On Mon, Feb 24, 2025 at 09:48 AM, Tony Casey wrote:

... The LTspice just takes the two closest data points and performs linear interpolation to establish when the expression is true. ...

That might be true.? But I distinctly recall Helmut Sennewald cautioning people not to test for equality.? Better to use >= or <=.? The implication was that it did not use linear interpolation in those situations.? I thought .MEAS was one of them.

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Perhaps I remembered incorrectly.

I think you're missing the point I made in the first response. This type of .MEAS is designed to find a single point on the x-axis when an expression is true. None of the .MEAS examples in the Help use any operator other than "=". Everything else is an inequality, which returns an interval.

E.g.:

.MEAS TRAN res6 WHEN V(x)=3*V(y)

Print the first time the condition V(x)=3*V(y) is met. This will be labeled res6.

.MEAS can perform a calculation over an interval, but still returns a single result.

Simple example of a sine wave source:

.MEAS T1 when V(test)=0
.MEAS T2 when V(test)<>0
.MEAS T3 when V(test)>=0
.MEAS T4 when V(test)<=0
.MEAS T5 when V(test)<0
.MEAS T6 when V(test)<0

Only T1 can return a single result:

LTspice 24.0.12 for Windows
Circuit: * U:\Simulations\LTspice\Lib\sub\Draft1.asc
Start Time: Mon Feb 24 16:20:42 2025
solver = Normal
Maximum thread count: 32
tnom = 27
temp = 27
method = modified trap
.OP point found by inspection.

t1: v(test)=0 AT 0

Measurement "t2" FAIL'ed

Measurement "t3" FAIL'ed

Measurement "t4" FAIL'ed

Measurement "t5" FAIL'ed

Measurement "t6" FAIL'ed

Total elapsed time: 0.051 seconds.

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... then it might remove the enforcing conditions and lets it converge again

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On Mon, Feb 24, 2025 at 09:30 AM, Tony Casey wrote:

So, try:

.MEAS TRAN T1 when V(XSW11:X1:Qc,XSW11:X1:Qe)=1 cross=1

I thought the general rule was to avoid testing with equalities.? That voltage will never be 1.00000000000000 exactly.

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But maybe I am confused or remember wrongly.

No, I think you're just introducing accuracy into the equality test. The LTspice just takes the two closest data points and performs linear interpolation to establish when the expression is true. It might not be absolutely correct. The smaller the time steps (or whatever the x-axis quantity is, because the same expression could be plotted in .DC analysis), the better the accuracy.

Whether the search criterion can be precisely expressed internally in binary format is another topic.

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When I put this on my schematc:

.MEAS TRAN TooLow1 find V(XSW11:X1:Qc,XSW11:X1:Qe) when V(XSW11:X1:Qc,XSW11:X1:Qe)<1

This .MEAS will fail because LTspice doesn't test for inequalities. It test for equalities. You are looking for a single instance in time - the answer cannot be an interval.

Assuming you can actually plot V(XSW11:X1:Qc,XSW11:X1:Qe), do you actually see any time when its value is less than 1?

Also, when you have complex expressions that fail, the procedure for debugging them is to simplify, so you can home in on which part is failing. "FAIL'ed diagnostic is not very helpful!

So, try:

.MEAS TRAN T1 when V(XSW11:X1:Qc,XSW11:X1:Qe)=1 cross=1

That will tell you when the expression is first true, but not the trajectory.

Or:

.MEAS TRAN T2 when V(XSW11:X1:Qc,XSW11:X1:Qe)=1 fall=1
.MEAS TRAN T3 when V(XSW11:X1:Qc,XSW11:X1:Qe)=1 rise=1

If both .MEASs succeed and T2 < T3, then V(XSW11:X1:Qc,XSW11:X1:Qe) < 1 between T2 and T3,

∴ T2 to T3 is your desired interval.

If T3 succeeds but not T2, then the expression is true from time = 0 to T3, but not afterwards.

You can extend the logic to find the other possibilities. If?V(XSW11:X1:Qc,XSW11:X1:Qe) is periodic, then there may be other intervals when the expression is true. .MEAS is not well suited to this kind of thing, although you can set the rise= or fall= qualifiers to different values in multiple .MEASs.

N.B. You could also plot:

if(V(XSW11:X1:Qc,XSW11:X1:Qe)<1,1,0)

..in a separate pane in the waveform viewer, which will plot multiple intervals when the expression is true. It sounds like this might be more useful for you.

--
Regards,
Tony

Be aware that LTspice's construct with an inductor having non-zero series resistance Rser, is a special implementation that did not exist in traditional SPICE.? I do not know (at least at this moment) how it is constructed internally and exactly what makes it behave the way that it does.? For all I know, it might be a Nortonized equivalent circuit, not a Thevenin (L+R in series), which would be consistent with the fact that the L+Rser does not add a node to the netlist.? "LTspice uses proprietary circuit simulation technology to simulate this physical inductor without any internal nodes."

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On the face of it, setting IC of L1 = 10, but also specifying UIC is paradoxical. I suppose IC = 10 doesn't count as an 'initial condition' despite the name. Evidence of this is the huge voltage spike at t = 0, which presumably is the way that the 10 A current is produced instantaneously.

On Mon, Feb 24, 2025 at 06:38 AM, Carlo wrote:

I1 0 v1 10
L1 v1 0 10u IC=10 Rser=1m
.tran 10n 1m uic
.ic V(v1)=0
.backanno
.end

Note that you neglected to include the Title line or command.? The first line of any SPICE Netlist that is suitable for running, is always ignored.

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You can copy-and-paste this netlist into a schematic.? But it should not be run by itself in batch mode, or results could be meaningless.

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I think you should stop quibbling about transient behavior when UIC is specified.? You may never get agreement between different SPICE programs about this, and you may not even get what seems to you to be sensible behavior from a nonsense simulation.? Be aware that LTspice's construct with an inductor having non-zero series resistance Rser, is a special implementation that did not exist in traditional SPICE.? I do not know (at least at this moment) how it is constructed internally and exactly what makes it behave the way that it does.? For all I know, it might be a Nortonized equivalent circuit, not a Thevenin (L+R in series), which would be consistent with the fact that the L+Rser does not add a node to the netlist.? "LTspice uses proprietary circuit simulation technology to simulate this physical inductor without any internal nodes."

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You seem to be very intent on trying to prove the behavior incorrect.? Please stop trying to do that.? You will only drive yourself (and us) crazy.

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Whenever UIC is used, results might appear to be incorrect.? Internal to LTspice, they are not.? FYI, this has been argued over 23 years of this group's existence.

I believe LTspice .TRAN UIC analysis's output at t=0 timestamp is actually garbage. Maybe Mike had a good reason for that, however I hope ADI will fix it in future releases.

I am sure it is not garbage, and it should not be changed.? But its understanding may be clouded and mysterious.

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Andy

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