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If I were placing a MOSFET e.g. W=5u L=0.5u , and the length of the source and drain implants might be LS=1u LD=1u. LS,LD could be defined with a .PARAM spice directive. In some netlisters, the

Dale, I don't know that there's much published in magazines/journals. Worldwide, there's very few people who work on SPICE internals these days. Books a largely a better source. I really like the 2nd

<mrose2@a...> wrote: function models. The rise and fall times default to 0 which will cause incorrect switching when the flops are cascaded. You have to add a Trise=xx value to the flop's Spiceline.

I just wanted to pass along a little tip when using DFLOP special function models. The rise and fall times default to 0 which will cause incorrect switching when the flops are cascaded. You have to

believe

Hello Steve, thanks for this fine example of using the rand-function. Arnold * *

What are some good magazines or journals to watch for info on circuit simulation, modeling, and SPICE? I can't find any publication that seems to concentrate on these topics. For example, the IEEE

As I said, it seemed a little strange to me, too. No need for assumptions. Let's just do the math. Back to the example, with slightly changed names (taken from my sheet of notes): ,-- V | | / &#92; R1

On Wed, 30 Apr 2003 19:41:15 -0000, you wrote: >--- In LTspice@..., Jonathan Kirwan <jkirwan@e...> wrote: >> On Sun, 27 Apr 2003 00:50:31 -0000, Helmut wrote: >> >> >Hello Jon, >> >sorry

--- In LTspice@..., Jonathan Kirwan <jkirwan@e...> wrote: > On Sun, 27 Apr 2003 00:50:31 -0000, Helmut wrote: > > >Hello Jon, > >sorry that I forgot to tell you that I assumed 50% duty

Hi. I've played around with this on paper for a bit, this morning. What came out is interesting, I think. Here's that circuit, again: ,-- V | | / &#92; R1 / | R2 | [Vnode] PWM >---/&#92;/&#92;/---x |

The "Edit Simulation Command" dialog box says: "Maximun Timestep:" where it should say: "Maximum Timestep:" Jon

Thanks for the help on the Table format. It is nice to get this kind of help and support.

Well, it all makes sense and it feels nice when everything goes together neatly and well. Probably all of this should go onto a web page or two, somewhere, with all the supporting work shown for those

Hello Jon, sorry that I forgot to tell you that I assumed 50% duty cycle. The absolute voltage ripple is at maximum for the 50% and thus it is a good formula for the worst case ripple estimation. My

Yes, I see. Thanks. So it's just a matter of "being too dumb" about what's been specified. It's up to me to tinker a little. Small price to pay. My RC is your tau and my tcyc is your Tpwm. I'm not

--- In LTspice@..., Jonathan Kirwan <jkirwan@e...> wrote: > On Sat, 26 Apr 2003 21:18:05 -0000, you wrote: > > >Hello Jon, > >please take a look(pobe) at your pulse source in LTSPICE. >

10%!! Egads. Okay. I see it! Thanks. Okay. I can see the issues much more clearly, now. Interesting. I used 1ns and it's much better. Thanks, again. I also tried dropping in 1ps, 10ps, and 100ps. What

--- In LTspice@..., Jonathan Kirwan <jkirwan@e...> wrote: > I've been just a little pensive about LT Spice accuracy. So > today I sat down with some paper and a relatively simple problem >

I've been just a little pensive about LT Spice accuracy. So today I sat down with some paper and a relatively simple problem and worked through some derivations to test LT Spice. Assume the following