--- In LTspice@..., "polapart" <sahawley@m...> wrote:
--- polapart <sahawley@m...> wrote:
I am trying to run a Burr Brown Op Amp, the OPA336.
The transient analysis "sort of" runs but LTSpice
notes a couple of problems, most notably
unrecognized parameters, jssw and vfb.
I couldn't find this model. Can you send it to me.
--Mike
Here's the link to the TI page. Thanks
genericPartNumber=OPA336&pfsection=models
Hello Steve,
the magic trick for the convergence problem in .AC analysis is the
latest 'gnin parallel current source' feature.
That was the only way I found to get convergence in .AC analysis for
this OPAMP.
Enable this feature in the control panel.
Control Panel->Hacks-> Add GMIN across current sorce
But this alone doesn't help. We have to add the command line
.OPTIONS gmin=1e-10 noopiter=1 into the schematic.
I have read in a book? that .TRAN analysis always does converge
better.
Hello Mike,
is that true?
Unfortunately this doesn't help anything when somebody has to make
a .AC analysis.
What's about this error message regarding JFET parameters?
Error on line 61 : .model nch nmos (level=3 tox=30e-9 cgdo=1.55e-10
cgso=1.55e-10 cj=6.300e-4 cjsw=3.83e-10 af=1.05 kf=2.6e-31 js=2.0e-7
jssw=5e-13 rsh=68 mj=.25 mjsw=.11 vfb=-0.784 phi=0.792 vto=.81 ld=34e-
9 wd=17e-9 tpg=-1 gamma=0.6)
Unrecognized parameter "jssw" - ignored
Unrecognized parameter "vfb" - ignored
Error on line 60 : .model pch pmos (level=3 tox=30e-9 cgdo=1.80e-10
cgso=1.80e-10 cj=7.199e-4 cjsw=3.40e-10 af=1.05 kf=1.0e-31 js=4.0e-7
jssw=3.0e-13 rsh=117 mj=.47 mjsw=.16 vfb=-0.34 phi=0.71 vto=-.892
ld=12e-9 wd=43e-9 tpg=+1 gamma=0.6)
Unrecognized parameter "jssw" - ignored
Unrecognized parameter "vfb" - ignored
I have my test files attached.
Best Regards
Helmut
The LTSPICE file for .AC analysis.
Version 4
SHEET 1 1372 1316
WIRE 320 320 320 352
WIRE 320 256 320 224
WIRE -16 368 -16 304
WIRE -16 96 80 96
WIRE 80 304 -16 304
WIRE 160 304 240 304
WIRE 160 96 240 96
WIRE 288 272 240 272
WIRE 240 272 240 96
WIRE 464 96 512 96
WIRE 512 96 512 288
WIRE 512 288 352 288
WIRE -16 480 -16 448
WIRE 240 480 240 512
WIRE 384 480 384 512
WIRE 240 592 240 624
WIRE 384 592 384 624
WIRE 512 288 544 288
WIRE 240 96 384 96
WIRE 240 304 288 304
WIRE 320 976 320 1008
WIRE 320 912 320 880
WIRE -16 752 96 752
WIRE 80 960 -16 960
WIRE 160 960 240 960
WIRE 160 752 240 752
WIRE 288 928 240 928
WIRE 240 928 240 752
WIRE 464 752 512 752
WIRE 512 752 512 944
WIRE 512 944 352 944
WIRE 512 944 544 944
WIRE 240 752 384 752
WIRE 240 960 288 960
WIRE -16 1024 -16 960
WIRE -16 1136 -16 1104
FLAG 320 224 Vcc
FLAG 240 480 Vcc
FLAG 384 480 Vss
FLAG 320 352 Vss
FLAG -16 480 0
FLAG 240 624 0
FLAG 384 624 0
FLAG 544 288 out
FLAG 240 96 in-
FLAG 240 304 in+
FLAG -16 96 0
FLAG 320 880 Vcc
FLAG 320 1008 Vss
FLAG 544 944 out1
FLAG 240 752 in1-
FLAG 240 960 in1+
FLAG -16 752 0
FLAG -16 304 in
FLAG -16 1136 0
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\x_models\xopamp 320 224 R0
SYMATTR InstName U1
SYMATTR Value OPA336
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\voltage 240 496 R0
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\voltage 384 496 R0
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\voltage -16 352 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V3
SYMATTR Value 1
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\res 368 112 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 1MEG
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\res 64 320 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R2
SYMATTR Value 1MEG
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\res 64 112 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R3
SYMATTR Value 1MEG
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\x_models\xopamp 320 880 R0
SYMATTR InstName U2
SYMATTR Value OPA336
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\res 368 768 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R4
SYMATTR Value 1MEG
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\res 64 976 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R5
SYMATTR Value 1
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\cap 96 768 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\voltage -16 1008 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V4
SYMATTR Value 0
TEXT -432 40 Left 0 ;.op
TEXT -432 -128 Left 0 !.include opa336.mod
TEXT -440 -160 Left 0 !.AC DEC 100 1 100MEG
TEXT -432 -40 Left 0 !.nodeset V(out)=2 V(in-)=1 V(in+)=1
TEXT -400 1256 Left 0 ;.OPTIONS vntol=1e-2 reltol=1e-2 itl1=500
itl2=500 itl6=500 abstol=1e-4 gmin=1e-9 gminsteps=100 noopiter=1
pivtol=1e-6
TEXT -432 -8 Left 0 !.nodeset V(out1)=0 V(in1-)=0 V(in1+)=0
TEXT -432 -88 Left 0 !.OPTIONS gmin=1e-10 noopiter=1
TEXT -400 1288 Left 0 ;.OPTIONS itl1=500 itl2=500 itl6=500 vntol=1e-
3 abstol=1e-12 reltol=1e-3 trtol=1 pivtol=1e-13 pivrel=1e-3 gmin=1e-
12 gminsteps=100 noopiter=1
The model OPA336.mod:
Be carefully with the broken lines I see in this awful YAHOO-editor.
* -------------------------------------------------------------------
-----
* | NOTICE: THE INFORMATION PROVIDED HEREIN IS BELIEVED TO BE
RELIABLE; |
* | HOWEVER; BURR-BROWN ASSUMES NO RESPONSIBILITY FOR INACCURACIES
OR |
* | OMISSIONS. BURR-BROWN ASSUMES NO RESPONSIBILITY FOR THE USE OF
THIS |
* | INFORMATION, AND ALL USE OF SUCH INFORMATION SHALL BE ENTIRELY
AT |
* | THE USER'S OWN RISK. NO PATENT RIGHTS OR LICENSES TO ANY OF
THE |
* | CIRCUITS DESCRIBED HEREIN ARE IMPLIED OR GRANTED TO ANY THIRD
PARTY. |
* | BURR-BROWN DOES NOT AUTHORIZE OR WARRANT ANY BURR-BROWN PRODUCT
FOR |
* | USE IN LIFE-SUPPORT DEVICES AND/OR
SYSTEMS. |
* -------------------------------------------------------------------
-----
*
*
*
* SUBCIRCUIT MACROMODEL OPA336
* PSpice ver. 6.3
* REV A. CREATED Wednesday, June 18, 1997 RH
* REV B. 25 JUNE 97 NPA: COMPILED INTO OPA336.MOD
* REV C. 26 JUNE 97 NPA: EDITED NODE SYNTAX AND ADDED .OPTION NOTES
*
* Notes concerning using macromodel to simulate OPA336:
* 1) Model is actually a simplified schematic of OPA336.
* 2) Model was created with PSpice ver. 6.3, level 3 device models.
* 3) Operation of the circuit is assumed to be single supply
*
* Example: X_U1 1 2 3 0 5 OPA336
*
* Where U is the subcircuit name and
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* .subckt OPA336 1 2 3 4 5
*
* Note that node "4" may be connected to ground "0", i.e., single
supply operation.
*
* 4) ADD .OPTION ITL=40 AND .OPTION GMIN=10p TO NET LIST IF
SIMULATION DOES NOT
* CONVERGE
* 5) ADDING .NODESET STATEMENT (BELOW) TO NET LIST MAY HELP
CONVERGENCE IS CASES
* WHERE V+=5V AND V-=0V ; SINGLE SUPPLY OPERATION. ASSUMES
SUBCIRCUIT IS "U1".
*
* .NODESET
* +V(2) = 2.5 V(1) = 2.5 V(5) = 2.5 V(3) = 5.0
* +V(X_U1.20)= 3.8 V(X_U1.23)= 3.8 V(X_U1.25)= .834 V(X_U1.27)
= .833 V(X_U1.29)= .834
* +V(X_U1.32)= 2.03 V(X_U1.34)= 2.03 V(X_U1.43)= 4.065 V(X_U1.44)=
2.51 V(X_U1.45)= 1.93
* +V(X_U1.47)= 1.93 V(X_U1.51)= .848 V(X_U1.53)= 4.07 V(X_U1.54)=
1.58 V(X_U1.55)= 4.02
* +V(X_U1.60)= 1.94 V(X_U1.62)= .855 V(X_U1.64)= 3.17 V(X_U1.67)=
4.98 V(X_U1.76)= 2.51
* +V(X_U1.GNDS)= 0.0 V(0)= 0.0
*
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
.subckt OPA336 1 2 3 4 5
*
M61 4 64 55 55 PCH W=20U L=0.8U M=1
M59 55 53 3 3 PCH W=15U L=5U M=4
M55 55 60 51 GNDS NCH W=5U L=0.8U M=1
M53 53 45 51 GNDS NCH W=5U L=0.8U M=1
M57 53 53 3 3 PCH W=15U L=5U M=2
C55 55 60 CP1P2 2P
M67 55 55 67 3 PCH W=5U L=5U M=1
M74 45 51 62 GNDS NCH W=5U L=1U M=1
R67 3 67 RNW 200K
R47 45 47 RPO2 2K
ITAIL 3 23 DC 6U AC 0
ITAIL2 27 4 DC 1.6U AC 0
ITAIL3 51 4 DC 0.8U AC 0
I60 3 60 DC 0.4U AC 0
RGNDS GNDS 4 0.01
M24 29 1 23 3 PCH W=90U L=2U AD=2560P PD=3328U AS=2688P
PS=3494U M=1
M26 29 27 4 GNDS NCH W=500U L=2U AD=1142P PD=1670U AS=1142P
PS=1670U M=1
I20 20 4 DC 1U AC 0
R20 3 20 1.2MEG
M20 4 20 23 3 PCH W=5U L=2U M=1
R32 32 25 1.2MEG
R34 34 29 1.2MEG
I34 3 34 DC 1U AC 0
I32 3 32 DC 1U AC 0
V64 3 64 DC 1.8302
V60 60 62 DC 1.0897
V62 62 4 DC .8547
M23 25 2 23 3 PCH W=90U L=2U AD=2560P PD=3328U AS=2688P
PS=3494U M=1
M47 43 43 3 3 PCH W=60U L=4U M=1
M43 43 34 27 GNDS NCH W=4U L=4U M=1
M45 45 32 27 GNDS NCH W=4U L=4U M=1
M73 76 51 4 GNDS NCH W=5U L=0.8U M=20
M25 25 27 4 GNDS NCH W=500U L=2U AD=1142P PD=1670U AS=1142P
PS=1670U M=1
M71 76 55 3 3 PCH W=20U L=0.8U M=20
M49 45 43 3 3 PCH W=60U L=4U M=1
RC1 44 76 RPO2 10K
R76 76 5 RPO2 100
CM1 29 44 CP1P2 200P
C45 47 76 CP1P2 22P
RC2 54 4 RPO2 10K
CM2 25 54 CP1P2 200P
.ENDS
* MODELS for LEVEL 3 PSpice
*
.MODEL PCH PMOS (LEVEL=3 TOX=30E-9 CGDO=1.80e-10 CGSO=1.80e-10
CJ=7.199E-4 CJSW=3.40E-10
+AF=1.05 KF=1.0e-31 JS=4.0e-7 JSSW=3.0e-13 RSH=117 MJ=.47 MJSW=.16
VFB=-0.34 PHI=0.71 VTO=-.892
+LD=12E-9 WD=43E-9 TPG=+1 GAMMA=0.6)
.MODEL NCH NMOS (LEVEL=3 TOX=30E-9 CGDO=1.55e-10 CGSO=1.55e-10
CJ=6.300E-4 CJSW=3.83E-10
+AF=1.05 KF=2.6e-31 JS=2.0e-7 JSSW=5e-13 RSH=68 MJ=.25 MJSW=.11 VFB=-
0.784 PHI=0.792 VTO=.81
+LD=34E-9 WD=17E-9 TPG=-1 GAMMA=0.6)
.MODEL RPO2 RES (R=1 TC1=6.3e-4 TC2= 1.1e-6)
.MODEL RNW RES (R=1 TC1=5.5e-3 TC2=-1.3e-5)
.MODEL CP1P2 CAP (C=1)
*.ENDS
*.ENDS OPA336
*