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Simulation of electromechanical system using LTSPICE

 

Hello,


I am fairly new with LTSPICE. I am trying to simulate an electromechanical system using LTSPICE and facing some problems. My system contains 2 subsystems : 1st for mechanical system, 2nd for electrical system.


Mechanical system is a complex mass spring damper system which upon an external vibration should oscillate and there is a change in capacitance (forms variable capacitance). I can do the electrical analogue of this.


Then the variable capacitance is used in the electrical system to simulate the overall system.?


There is a paper which does it using behavioral sources. The link of the paper is given below.




If anyone has any idea on how such system can be solved, it will be great if you could help me on this. I can discuss further.


Thank you very much
Re: DSBSC

 

Bordodynov wrote:

? ?"See file Modulator.asc in TEMP folder."

?Bordodynov, I am trying to figure out exactly what your circuit does.

What is the parameter 'm'?

Andy
Re: DSBSC

 

? ?"Doing that requires changing two frequencies if you want a different ¡°carrier¡± frequency."

It does.

Easily handled by using .PARAMs and a little bit of math.

Andy

?
Re: DSBSC

 

¿ªÔÆÌåÓý

Doing that requires changing two frequencies if you want a different ¡°carrier¡± frequency.

Jim

James Wagner
Oregon Research Electronics



On Aug 17, 2016, at 2:24 AM, Gunoi Nare gunoiar@... [LTspice] <LTspice@...> wrote:


Great minds think alike :)

"There is a third option, which would be to generate the two sideband signals directly, using two SINE sources and adding them together."

this is just what I am trying now.It is not perfect but it works.

Thanks,Andy.

G





From:?"Andy?ai.egrps@...?[LTspice]" <LTspice@...>
To:?[LTspice] group <LTspice@...>?
Sent:?Tuesday, August 16, 2016 11:20 AM
Subject:?Re: [LTspice] DSBSC

?
Gunoi Nare?wrote:

? ?"To my surprise I can not find a LTC multiplier."

I would not use a real analog multiplier IC, if all I wanted was to simulate a double-sideband suppressed-carrier signal.

(FYI, I am also not aware of a general purpose linear 4-quadrant multiplier made by LTC, similar to the ones Analog Devices makes.? The two companies' product lines do not totally overlap -- which is why ADI was interested in acquiring LTC.)

Instead, use the multiplication function from a more primitive SPICE element.

I think you have two main choices.? One is to use the Modulate or Modulate2, as Helmut suggested.? Yes, it does suppress the carrier, if the amplitude (AM) input is sinusoidal with zero offset.? The output amplitude follows the voltage of the AM input pin.? When that voltage goes negative, the output amplitude also goes negative (becomes inverted).? The net result is cancellation of the carrier component.

The other choice, is to make a B behavioral source, with a formula that includes multiplication.? B-elements are very flexible, letting you make just about any kind of signal if you can express it in a formula. ?(You could instead use one of the traditional SPICE controlled sources = E, F, G, or H, but they are somewhat more difficult to use.)

There is a third option, which would be to generate the two sideband signals directly, using two SINE sources and adding them together.

Andy
Re: DSBSC

 

Hi.
See file Modulator2.asc in TEMP folder.

Bordodynov.
Re: DSBSC

 

Gunoi Nare wrote:

? ?"this is just what I am trying now.It is not perfect but it works."

I am wondering why you say it is not perfect.

If you have the frequencies and their phases right, it ought to be perfect.? In fact the phases don't really matter, except in a relative way.

Of course we are always dealing with sampled data, so there are imperfections due to that fact (which can be reduced by changing the sampling rate, to the degree that we have control over it).

Andy
Re: DSBSC

 

Hi.
See file Modulator.asc in TEMP folder.

Bordodynov.

17.08.2016, 12:24, "Gunoi Nare gunoiar@... [LTspice]" <ltspice@...>:

Great minds think alike :)

"There is a third option, which would be to generate the two sideband signals directly, using two SINE sources and adding them together."

this is just what I am trying now.It is not perfect but it works.

Thanks,Andy.

G

----------------------------------------
From: "Andy ai.egrps@... [LTspice]" <LTspice@...>
To: [LTspice] group <LTspice@...>
Sent: Tuesday, August 16, 2016 11:20 AM
Subject: Re: [LTspice] DSBSC

Gunoi Nare wrote:

? ?"To my surprise I can not find a LTC multiplier."

I would not use a real analog multiplier IC, if all I wanted was to simulate a double-sideband suppressed-carrier signal.

(FYI, I am also not aware of a general purpose linear 4-quadrant multiplier made by LTC, similar to the ones Analog Devices makes.? The two companies' product lines do not totally overlap -- which is why ADI was interested in acquiring LTC.)

Instead, use the multiplication function from a more primitive SPICE element.

I think you have two main choices.? One is to use the Modulate or Modulate2, as Helmut suggested.? Yes, it does suppress the carrier, if the amplitude (AM) input is sinusoidal with zero offset.? The output amplitude follows the voltage of the AM input pin.? When that voltage goes negative, the output amplitude also goes negative (becomes inverted).? The net result is cancellation of the carrier component.

The other choice, is to make a B behavioral source, with a formula that includes multiplication.? B-elements are very flexible, letting you make just about any kind of signal if you can express it in a formula. ?(You could instead use one of the traditional SPICE controlled sources = E, F, G, or H, but they are somewhat more difficult to use.)

There is a third option, which would be to generate the two sideband signals directly, using two SINE sources and adding them together.

Andy
Re: DSBSC

Gunoi Nare
 

Great minds think alike :)

"There is a third option, which would be to generate the two sideband signals directly, using two SINE sources and adding them together."

this is just what I am trying now.It is not perfect but it works.

Thanks,Andy.

G





From: "Andy ai.egrps@... [LTspice]"
To: [LTspice] group
Sent: Tuesday, August 16, 2016 11:20 AM
Subject: Re: [LTspice] DSBSC

?
Gunoi Nare wrote:

? ?"To my surprise I can not find a LTC multiplier."

I would not use a real analog multiplier IC, if all I wanted was to simulate a double-sideband suppressed-carrier signal.

(FYI, I am also not aware of a general purpose linear 4-quadrant multiplier made by LTC, similar to the ones Analog Devices makes.? The two companies' product lines do not totally overlap -- which is why ADI was interested in acquiring LTC.)

Instead, use the multiplication function from a more primitive SPICE element.

I think you have two main choices.? One is to use the Modulate or Modulate2, as Helmut suggested.? Yes, it does suppress the carrier, if the amplitude (AM) input is sinusoidal with zero offset.? The output amplitude follows the voltage of the AM input pin.? When that voltage goes negative, the output amplitude also goes negative (becomes inverted).? The net result is cancellation of the carrier component.

The other choice, is to make a B behavioral source, with a formula that includes multiplication.? B-elements are very flexible, letting you make just about any kind of signal if you can express it in a formula. ?(You could instead use one of the traditional SPICE controlled sources = E, F, G, or H, but they are somewhat more difficult to use.)

There is a third option, which would be to generate the two sideband signals directly, using two SINE sources and adding them together.

Andy
Re: Benchmarking the new LTspice

 

? ?"I assume everyone was testing with 64 bit LTspice XVII or they would have noted otherwise."

I think there are a lot of people with 64-bit CPUs, running 32-bit Windows, who do not realize it.

The people on this group are at least a little more aware than most.? Still, the possibility exists that they might not know if they are limited to 32-bit programs on their 64-bit-capable hardware.? Windows doesn't exactly jump out and tell you when it cripples your computer like that.

Andy
Re: noiseless resistor

 

Yesterday I wrote that -1E308 dB was numeric underflow, but that's wrong.? Actually it is overflow, with a negative number.? Sorry.

Andy
Re: Benchmarking the new LTspice

ehydra
 

I miss a lengthy statement about performance issues from Mike. Surely he did longer tests to optimize the decision algorithm. So he knows enought to guide us but he won't or I missed it.

What I know is that in the change history there was a mention of 'optimized for I7' or something. So at least for a short time that looks like the in-house basic CPU for simulations.
We know Mike change LTspice very fast if he decide there is a need to do so. Looking for the time this particular CPU was issued and when the history file filed the revision should give some approximation how much money LTC in average spent for a workstation pc doing simulation work. After this one can stipulate how near is LTC at the 'performance front' of Intel is. (There was a mention that LTspice is optimized for Intel and not for AMD)

- H.
Re: Benchmarking the new LTspice

 


Hi Andy,

This was an informal exercise just to help me chose a new home computer optimized for LTspice. :-)? Except for my old Pentium D, which was XP 32 bit LTspice IV, I assume everyone was testing with 64 bit LTspice XVII or they would have noted otherwise.

My new home computer will most likely be running Windows 7, 64 bit with LTspice XVII on some sort of i7-Extreme, probably 8 cores running at 4+GHz.? I have copied a conversation with Orbital Computer below.? His test results are not as good as expected, probably because the test simulation is not complex enough to reap the full benefit of more cores.
______________________________________________________________

Unless I'm missing some setting other than the three you want changed,
I'm only getting 76 to 82 seconds on 6 core 12 thread and 10 core 20
thread systems running at 4.40 GHz and 4.00 GHz respectively.

I would expect results about 35% faster than the 1620 v3, based simply
on benchmark comparisons of those two CPUs.? There may be some form of a
software or simulation-specific bottleneck that's holding things up.
---
Best Regards,
Danny Payne
Orbital Computers LLC

877-976-7510


On 2016-08-16 01:40 PM, analogspiceman wrote:
> When LTspice first runs it tests the hardware upon which it is running
> so that it can decide how many cores may be effectively used based on
> the size of the simulation.? If the simulation is too small, it won't
> use all the cores.? There also may be an upper limit of 8 cores just
> because the guy who wrote the software did not think anyone would have
> more.? However, he constantly improves and upgrades the software to
> meet user requests and to work best with the latest hardware (one of
> LTspice's drop down menu items is to run a software update from the
> web -- these are typically available every few weeks, but when I have
> reported a true bug, sometimes an update will be available within a
> couple of hours).
>
> Many of the simulation I run are larger than the one we are testing,
> but it seems that an 8-core i7 Extreme with double fan cooling is a
> sweet spot right now.? Here is the configuration for the tests the
> way I have asked some of the users group members to run the test
> (three changes from standard):
>
> The Alternate Solver must be selected (pull down menu item), Reltol
> must be relaxed to = 0.01 and Trtol must be set to 7 (click the Hammer
> icon to access the Control Panel and then click the Hammer tab to
> access the SPICE settings).
>
> And here are some of the results and my prediction for your machine.
>
> Cores Clock Processor, Memory, Disk: Time
>
> (2/2) 3.00GHz Pentium D-930, 2GB, HD: 451s (my old home Gateway tower)
> (4/8) 1.73GHz Core i7-820QM, 4GB, HD: 246s (my old home Lenovo laptop)
> (2/4) 2.70GHz Core i5-5200u, 4GB, HD: 145s (PhB's newish laptop)
> (4/8) 3.40GHz Xeon E3-1240 v3, 8GB, SSD: 126s (my HP office computer)
> (4/8) 3.50GHz Xeon E5-1620 v3, ?GB, SSD?: 91s (Helmut's office computer)
>
> (8/16) 4.20GHz Core i7-Extreme, 32GB, SSD: ~40s? (a new high performance
> tower from Orbital Computer)
>
> The last guess assumes that LTspice would use all of the cores (this
> simulation may be too small for that).
>
> On Tuesday, August 16, 2016 11:46 AM, Orbital Computers
> <support@...> wrote:
>
> Ok so I just finished the test as specified and the SPICE Error Log
> reports a total elapsed time of 76.443 seconds.



---In LTspice@..., <ai.egrps@...> wrote :

analogspiceman wrote:

? ?"Cores Clock Processor, Memory, Disk: Time

? ? (2/2) 3.00GHz Pentium D-930, 2GB, HD: 451s (my old home tower)
? ? ..."

?But you are not tracking which versions (LTspiceIV or LTspiceXVII, 32-bit, or 64-bit), are you?

It makes a difference; at least the latter two do.

Andy


?
Re: Benchmarking the new LTspice

 

analogspiceman wrote:

? ?"Cores Clock Processor, Memory, Disk: Time

? ? (2/2) 3.00GHz Pentium D-930, 2GB, HD: 451s (my old home tower)
? ? ..."

?But you are not tracking which versions (LTspiceIV or LTspiceXVII, 32-bit, or 64-bit), are you?

It makes a difference; at least the latter two do.

Andy
Re: Benchmarking the new LTspice

 

Mike claims that LTspice tests the hardware performance of each machine on which it runs and then decides for each simulation how many of the available cores and threads is worth the additional overhead.? It seems that Mike has learned how to reduce overhead so that running more cores has become very efficient for LTspice.

The new Intel Xeon Phi Processor 7230 (16GB, 1.30 GHz) has 64 cores / 256 threads (and costs $4k!!).? GPUs have thousands of cores and are trending to becoming electronic simulation capable.? A lot of work has been going into understanding how to effectively use parallel processing (this includes making electronic brain-like neural networks - the positronic brain anyone?).


---In LTspice@..., <allanvv@...> wrote :

Indeed, there are Xeons that have 20+ cores that you would be paying $10k+ for. However, I don't think you would be gaining much speed by splitting a simulation into even more threads, and in fact you would be losing it due to the overheads. So cores*clock speed might be the relevant factor, but upping the cores to 12 while keeping the cores*freq product the same makes your CPU cost way more for no performance gain. I originally did recommend getting a 6-8 core CPU but overclocking it regardless. You can actually set a different clock speed for 1 core use or 6 core use, since the limiting factor is TDP.

On Tue, Aug 16, 2016 at 2:30 PM, analogspiceman@... [LTspice] <LTspice@...> wrote:


Allan,

What you wrote only applies to small simulations that generally run very fast anyway.? The typical large simulation that I run at work will max out all four cores and eight threads available to me, so for real work simulations, it is possible that by doubling the core and thread count, I might nearly double simulation speed.? It seems the trend for the design of newest processors has bifurcated into tradition designs (faster clock speeds and a only few cores) and those with dozen or even hundreds of cores.? It seems that Mike Engelhardt (LTspice's author) has become very proficient at writing code to take advantage of more cores.


---In LTspice@..., <allanvv@...> wrote :

Your simulation speed will be directly proportional to the clock speed. The CPU speed is the bottleneck after all,?

If your CPU turbo boosts to 3.8 GHz (one core), and you overclock to 4.4 GHz, then you should gain around 15%.

On Tue, Aug 16, 2016 at 5:03 AM, basier.philippe@... [LTspice] <LTspice@...> wrote:


Hello allan

You wrote :
" My recommendation is to buy a good desktop CPU with 6-8 cores, buy a gigantic $50 CPU fan (Noctua), and overclock your CPU. "

I seriously doubt that somebody could gain a lot of time running LTspice, even in 0.1%,? with overclocking.

Regards
PhB





?
Re: Benchmarking the new LTspice

Allan Wang
 

Indeed, there are Xeons that have 20+ cores that you would be paying $10k+ for. However, I don't think you would be gaining much speed by splitting a simulation into even more threads, and in fact you would be losing it due to the overheads. So cores*clock speed might be the relevant factor, but upping the cores to 12 while keeping the cores*freq product the same makes your CPU cost way more for no performance gain. I originally did recommend getting a 6-8 core CPU but overclocking it regardless. You can actually set a different clock speed for 1 core use or 6 core use, since the limiting factor is TDP.

On Tue, Aug 16, 2016 at 2:30 PM, analogspiceman@... [LTspice] <LTspice@...> wrote:


Allan,

What you wrote only applies to small simulations that generally run very fast anyway.? The typical large simulation that I run at work will max out all four cores and eight threads available to me, so for real work simulations, it is possible that by doubling the core and thread count, I might nearly double simulation speed.? It seems the trend for the design of newest processors has bifurcated into tradition designs (faster clock speeds and a only few cores) and those with dozen or even hundreds of cores.? It seems that Mike Engelhardt (LTspice's author) has become very proficient at writing code to take advantage of more cores.


---In LTspice@..., wrote :

Your simulation speed will be directly proportional to the clock speed. The CPU speed is the bottleneck after all,?

If your CPU turbo boosts to 3.8 GHz (one core), and you overclock to 4.4 GHz, then you should gain around 15%.

On Tue, Aug 16, 2016 at 5:03 AM, basier.philippe@... [LTspice] <LTspice@...> wrote:


Hello allan

You wrote :
" My recommendation is to buy a good desktop CPU with 6-8 cores, buy a gigantic $50 CPU fan (Noctua), and overclock your CPU. "

I seriously doubt that somebody could gain a lot of time running LTspice, even in 0.1%,? with overclocking.

Regards
PhB
Re: Benchmarking the new LTspice

 

Allan,

What you wrote only applies to small simulations that generally run very fast anyway.? The typical large simulation that I run at work will max out all four cores and eight threads available to me, so for real work simulations, it is possible that by doubling the core and thread count, I might nearly double simulation speed.? It seems the trend for the design of newest processors has bifurcated into tradition designs (faster clock speeds and a only few cores) and those with dozen or even hundreds of cores.? It seems that Mike Engelhardt (LTspice's author) has become very proficient at writing code to take advantage of more cores.


---In LTspice@..., <allanvv@...> wrote :

Your simulation speed will be directly proportional to the clock speed. The CPU speed is the bottleneck after all,?

If your CPU turbo boosts to 3.8 GHz (one core), and you overclock to 4.4 GHz, then you should gain around 15%.

On Tue, Aug 16, 2016 at 5:03 AM, basier.philippe@... [LTspice] <LTspice@...> wrote:


Hello allan

You wrote :
" My recommendation is to buy a good desktop CPU with 6-8 cores, buy a gigantic $50 CPU fan (Noctua), and overclock your CPU. "

I seriously doubt that somebody could gain a lot of time running LTspice, even in 0.1%,? with overclocking.

Regards
PhB
Re: Benchmarking the new LTspice

Allan Wang
 

Your simulation speed will be directly proportional to the clock speed. The CPU speed is the bottleneck after all,?

If your CPU turbo boosts to 3.8 GHz (one core), and you overclock to 4.4 GHz, then you should gain around 15%.

On Tue, Aug 16, 2016 at 5:03 AM, basier.philippe@... [LTspice] <LTspice@...> wrote:


Hello allan

You wrote :
" My recommendation is to buy a good desktop CPU with 6-8 cores, buy a gigantic $50 CPU fan (Noctua), and overclock your CPU. "

I seriously doubt that somebody could gain a lot of time running LTspice, even in 0.1%,? with overclocking.

Regards
PhB


Re: Calculation of the inductance of the amplitude of the first harmonic voltage and current amplitude

 

Hi.
The fact that I am interested in the behavior of inductors and at the approach to saturation. Usually, lead ferrite losses at the induction B = 0.2Tesla. This is already affecting the core nonlinearity. I did modeling for N41 material. In the current transformer, according to my calculations, there is a decrease in gain with increasing current up to 100A by ~ 0.33%. This occurs due to nonlinearity.

Bordodynov.

16.08.2016, 16:43, "Michael Peter Nekambuza Kiwanuka michael883575@... [LTspice]" <ltspice@...>:

Hi,

I thought he Inductance of an inductor is independent of the amplitude of the driving signal assuming you don't saturate the core. ?Please correct me If I am wrong.

Michael

----------------------------------------
To: ltspice@...
From: LTspice@...
Date: Tue, 16 Aug 2016 10:54:33 +0300
Subject: Re: [LTspice] Calculation of the inductance of the amplitude of the first harmonic voltage and current amplitude

Vlad,
I added one more circuit. And I asked the question. See my other letter!
And see the file four_ways_to_determine_the_inductance.zip.

Bordodynov.

16.08.2016, 10:35, "Vlad imbvlad@... [LTspice]" <ltspice@...>:
I think not the average, and calculate the amplitude of the first harmonic. I made a parallel Fourier analysis. Look at the first harmonic and what I counted. The values are the same, with sufficient accuracy for practical purposes.
Yes, the resultant is the amplitude, after multiplying the average -- the idt(...) term -- with 2. If, instead of idt(...)*2*f, you write idt(...)*f, you get the average, or half the amplitude, since you are calculating for the fundamental, only. At any rate, your calculations look correct, to me.

Vlad
______________________
ltspicegoodies.ltwiki.org -- holding, among others:
a universal analog/digital filter, block-level models
for power electronics (and not only), math blocks
with a more stream-lined approach, some digital
ADC, DAC, (synchronous-)counter, JKflop, etc.
Re: noiseless resistor

 

? ?"- 1E308 dB"

That is essentially numeric underflow.? There is no number to show negative infinity decibels, and the logarithm (decibel calculation) of zero, is negative infinity.

A little more about the handling of numbers in LTspice can be found here:



Andy
Re: DSBSC

 

Gunoi Nare wrote:

? ?"To my surprise I can not find a LTC multiplier."

I would not use a real analog multiplier IC, if all I wanted was to simulate a double-sideband suppressed-carrier signal.

(FYI, I am also not aware of a general purpose linear 4-quadrant multiplier made by LTC, similar to the ones Analog Devices makes.? The two companies' product lines do not totally overlap -- which is why ADI was interested in acquiring LTC.)

Instead, use the multiplication function from a more primitive SPICE element.

I think you have two main choices.? One is to use the Modulate or Modulate2, as Helmut suggested.? Yes, it does suppress the carrier, if the amplitude (AM) input is sinusoidal with zero offset.? The output amplitude follows the voltage of the AM input pin.? When that voltage goes negative, the output amplitude also goes negative (becomes inverted).? The net result is cancellation of the carrier component.

The other choice, is to make a B behavioral source, with a formula that includes multiplication.? B-elements are very flexible, letting you make just about any kind of signal if you can express it in a formula. ?(You could instead use one of the traditional SPICE controlled sources = E, F, G, or H, but they are somewhat more difficult to use.)

There is a third option, which would be to generate the two sideband signals directly, using two SINE sources and adding them together.

Andy
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