Re: AKO: Fails When Placed in Sub-Schematic
Use:
.model LoBT5551 ako:MMBT5551 NPN (Bf=80)
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AKO: Fails When Placed in Sub-Schematic
Hello All:
?
I have discovered that the spice statement ".model LoBT5551 ako:MMBT5551 Bf=80" fails if placed on a sub-schematic where the "LoBT5551" transistor is located.
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LTspice 24.0.12 says "Can't find definition of model LoBT5551".
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Moving the AKO: statement to the top-level schematic works as expected.
?
All for now
?
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Re: Any Good Reason to Create a Hierarchical Connector and Conductors to Route (Plumb) Ground Out of a Hierarchical Schematic
Hello eetech00:
?
Break a huge schematic that has grown so large it can't be easily read from one monitor into a dozen sub-schematics.
Those sub-schematics now have grounds peppered all around.
This lead me to the question which is the title of this thread.
?
I did not intend to add grounds.
I wanted to understand the ramifications of leaving those to-be-hidden grounds behind, or routing ground out of the hierarchical schematic to be connected on a top level schematic.
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After these discussions, I understand the need to remove all triangular (label 0) ground symbols from the interior of a hierarchical block and physically connect any nets that may have been disconnected by those ground symbol removals.
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I discovered first hand those confusing probe readings within a sub-circuit as detailed in my have a look here submission. ?
All for now
?
Sent:?Saturday, February 08, 2025 at 10:14 AM
From:?"eetech00 via groups.io" <eetech00@...>
To:[email protected]
Subject:?Re: [LTspice] Any Good Reason to Create a Hierarchical Connector and Conductors to Route (Plumb) Ground Out of a Hierarchical Schematic
On Fri, Feb 7, 2025 at 11:28 PM, eewiz wrote:
Hello All:
?
eetech00 wrote:
"Can you provide a simple example that demonstrates why you to have to run the sim multiple times?"
?
Instructions are on the schematic.
?
All for now
?
HI eewiz
?
I see what you've explained.
But in my humble opinion, it appears to be caused by a misuse of labels. When you add a ground symbol, you are basically adding a reserved label named "0" (zero). It has been known for years that a net should not have multiple dis-similar labels.
What is the intent of internally grounding the RTN pin?
?
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Re: Zener diode stabilizer
I did earlier suggest a "proper" regulator would be much better
idea, especially because of the load current. In general, people
need to be allowed to come their own conclusion. If you can't make
something work, it generally turns out it's because it was wrong
"solution".
--
Regards,
Tony
On 08/02/2025 18:35, John Woodgate
wrote:
toggle quoted message
Show quoted text
We
don't often see difficult English words here, and Google Translate
is usually quite accurate even with technical texts. Other
translators may also be good, but I haven't tested. I think the OP
has gone down a wrong path.
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Re: Zener diode stabilizer
We don't often see difficult English words
here, and Google Translate is usually quite accurate even with
technical texts. Other translators may also be good, but I
haven't tested. I think the OP has gone down a wrong path.
On 2025-02-08 17:12, Andy I via
groups.io wrote:
It is possible this is a language processing problem.? Being
from continental Europe, most likely English is not her/his
native language.
?
Either that, or she/he does not want to listen to advice, and
is stuck on one path and unwilling to consider changing.
?
Andy
?
?
--
OOO - Own Opinions Only
Best Wishes
John Woodgate
Keep trying
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Re: Zener diode stabilizer
It is possible this is a language processing problem.? Being from continental Europe, most likely English is not her/his native language.
?
Either that, or she/he does not want to listen to advice, and is stuck on one path and unwilling to consider changing.
?
Andy
?
?
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Re: LTSPICE SAVEBIAS Issue
BobT,
?
Can you either upload your entire simulation to the group's Temp folder, or tell us exactly what the error messages say?? Error messages sometimes come in pairs, or with a more descriptive line after the one announcing the error.? We can't tell what is happening without more information.? (Remember to carefully read and follow the guidelines on the group's main webpage.) ?
Definitely let us know which version of LTspice you used.? If it is 24.1.*, avoid it.? Downgrade to a better (older) version.? Analog Devices really messed up the latest versions and it should not be used.
?
Andy
?
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Re: Zener diode stabilizer
I pointed him to a capacitor, but he didn't
take it up. I can't even guess at what he's doing with a
large-ish sine wave superimposed on the DC supply.
On 2025-02-08 16:55, Andy I via
groups.io wrote:
Why are you using a
zener for this purpose in this circuit?? It is not the best choice
for smoothing the sine wave ripple.
--
OOO - Own Opinions Only
Best Wishes
John Woodgate
Keep trying
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Re: Zener diode stabilizer
On Sat, Feb 8, 2025 at 05:29 AM, jacfev wrote:
Diagram modified based on Tony's comments
Stabilisateur Zener_3.asc
Run simulation.
?
Move mouse pointer over D1 (zener) until the pointer turns into the funny ammeter icon, and click.? This plots the current through the zener.
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Most of it is negative current because zeners conduct in the "backwards" direction when they break down.? But notice that the current drops to zero over a significant part of the waveform.
?
When the current through the zener is zero, it is not doing anything to help.? In order for a zener to do anything helpful, anything at all, there needs to be current through it.? Being an open-circuit (non-conducting) in that portion of the waveform is no benefit, no help, no stabilization.
?
Plot V(R2).? Notice how that waveform is squashed (somewhat flattened) over part of the cycle, only in the part where the zener does conduct.? But it is pointy and not regulated (not stabilized) where the zener does not conduct.? Overall, it helps a little, but not as much as it should.
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Please read what Jerry Lee Marcel wrote.
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Why are you using a zener for this purpose in this circuit?? It is not the best choice for smoothing the sine wave ripple.
?
Andy
?
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On Sat, Feb 8, 2025 at 03:46 AM, Richard Lee wrote:
Is this the OnSemi datasheet on BSS84?
Yes.
?
?
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Re: Any Good Reason to Create a Hierarchical Connector and Conductors to Route (Plumb) Ground Out of a Hierarchical Schematic
I agree: I think there should be no ground
symbols inside the subcircuits. Of course, if you want to
simulate the subcircuit in isolation, a ground symbol is
necessary, but I would hang it on the RTN, so as to highlight
its temporary use.
On 2025-02-08 15:14, eetech00 via
groups.io wrote:
On Fri, Feb 7, 2025 at 11:28 PM, eewiz wrote:
Hello All:
?
eetech00 wrote:
"Can you provide a simple
example that demonstrates why you to have to run the sim
multiple times?"
?
Instructions are on the schematic.
?
All for now
?
HI eewiz
?
I see what you've explained.
But in my humble opinion, it appears to be caused by a misuse
of labels. When you add a ground symbol, you are basically
adding a reserved label named "0" (zero). It has been known for
years that a net should not have multiple dis-similar labels.
What is the intent of internally grounding the RTN pin?
?
--
OOO - Own Opinions Only
Best Wishes
John Woodgate
Keep trying
|
Re: Any Good Reason to Create a Hierarchical Connector and Conductors to Route (Plumb) Ground Out of a Hierarchical Schematic
On Fri, Feb 7, 2025 at 11:28 PM, eewiz wrote:
Hello All:
?
eetech00 wrote:
"Can you provide a simple example that demonstrates why you to have to run the sim multiple times?"
?
Instructions are on the schematic.
?
All for now
?
HI eewiz
?
I see what you've explained.
But in my humble opinion, it appears to be caused by a misuse of labels. When you add a ground symbol, you are basically adding a reserved label named "0" (zero). It has been known for years that a net should not have multiple dis-similar labels.
What is the intent of internally grounding the RTN pin?
?
|
Re: Zener diode stabilizer
You haven't answered any of the basic questions regarding source
capability and load expectations.
As it is, your circuit doesn't perform well, because between about
115¡ã and 160¡ã of the waveform, there is no current through the
zener.
Le 08/02/2025 ¨¤ 11:29, jacfev via
groups.io a ¨¦crit?:
toggle quoted message
Show quoted text
Diagram modified based on Tony's comments
Stabilisateur Zener_3.asc
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For example, looking at onsemi's datasheet, they show a 12:1 variation in transconductance between typical and minimum, and the maximum is unbounded.? It shows a 9:1 difference in Rds between maximum and typical, with an unknown/unbounded minimum Rds.? Even Idss has a 4:1 difference as a result of Tj, everything else being the same.
Thanks for this Andy.
?
Is this the OnSemi datasheet on BSS84?
?
I posted stuff in Temp and also in Photos.? I'll tidy things up and do a ZIP file with all included models too.
?
?
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Re: Any Good Reason to Create a Hierarchical Connector and Conductors to Route (Plumb) Ground Out of a Hierarchical Schematic
Hello All:
?
eetech00 wrote:
"Can you provide a simple example that demonstrates why you to have to run the sim multiple times?"
?
Instructions are on the schematic.
?
All for now
?
Sent:?Saturday, February 08, 2025 at 12:07 AM
From:?"eetech00 via groups.io" <eetech00@...>
To:[email protected]
Subject:?Re: [LTspice] Any Good Reason to Create a Hierarchical Connector and Conductors to Route (Plumb) Ground Out of a Hierarchical Schematic
On Tue, Feb 4, 2025 at 11:06 PM, eewiz wrote:
Hello All:
?
When no hierarchy is involved:
A resistor grounded on both ends is removed from the netlist hence, it shows no "plot my current" arrow when pointed at.
A resistor grounded on one end with the other end unconnected or connected to an open wire, is also removed from the netlist.
Neither resistor's current nor the open net's voltage can be plotted.
?
I tried a simple flat schematic containing a voltage source, V1 and two resistors, R1, R2. (I'm using 24.0.12)
?
If R2 is a resistor grounded on both ends, it remains in the net list, but is connected to 0 at both ends.
I(R2) cannot be plotted, and both ends of R2 report "This is ground".
?
V1 VCC 0 1
R1 VCC 0 1
R2 0 0 1
.tran 1
.backanno
.end
?
If R2 is a resistor grounded one end and open wire on the other, it remains in the net list, but is connected to 0 at one end and a unique net name on the other. I(R2) can be plotted, but it will be 0nA.
?
V1 VCC 0 1
R1 VCC 0 1
R2 0 N001 1
.tran 1
.backanno
.end
?
If R2 is a resistor grounded one end and open on the other, it remains in the net list, but is connected to 0 at one end, and a no-connection name "NC_01" on the other. I(R2) can be plotted, but it will be 0nA.
?
V1 VCC 0 1
R1 VCC 0 1
R2 0 NC_01 1
.tran 1
.backanno
.end
?
But it all cases, resistor R2 remains in the net list.
Can you provide a simple example that demonstrates why you to have to run the sim multiple times?
?
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Re: LTSPICE SAVEBIAS Issue
Which version of LTspice are you using? Any
'24.1.x' is not working properly and should not be used.
On 2025-02-08 03:51, Robert Tomlinson
via groups.io wrote:
I have a very large PWM controlled Power Supply Circuit with
dual outputs and It has been working fine until I added some new
circuits as loads.? Since it takes a long time to reach
steady-state operation, I usually simulate with some part value
changes that allow it to come up faster.? Then, I use SAVEBIAS
to create a file, that is used with UIC and LOADBIAS to
kick-start the simulation for the correct value components,
changes in loads, etc.
?
Recently, when I the file is ised with LOADBIAS it seems to
use the file, but when I look at the Output file, it says,
"Error: .nodeset syntax error."? I did not do anything with the
file and used it exactly as SAVEBIAS created it.? I have a lot
of Matrix Singularity issues with lots of nodes and wonder, if
it is because the LOADBIAS is using some of the file and not all
of it?
?
I looked in the discussions and only found something from a
much earlier version of LTSPICE.? Something about incorrect use
of the "#" sign in the file.
?
Any thoughts?
?
Thanks!
?
-BobT
--
OOO - Own Opinions Only
Best Wishes
John Woodgate
Keep trying
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Re: Any Good Reason to Create a Hierarchical Connector and Conductors to Route (Plumb) Ground Out of a Hierarchical Schematic
On Fri, Feb 7, 2025 at 10:03 PM, eewiz wrote:
Who desires to have to run a long simulation twice because the software maker could/would not make sub-circuit probing work correctly on the first run?
Like I said, this is an LTspice bug.? It is a somewhat obscure bug so getting it serviced could be challenging.
?
I do not doubt that one should avoid having this situation in a lower-level schematic, BTW.
?
Andy
?
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Re: Any Good Reason to Create a Hierarchical Connector and Conductors to Route (Plumb) Ground Out of a Hierarchical Schematic
On Tue, Feb 4, 2025 at 11:06 PM, eewiz wrote:
Hello All:
?
When no hierarchy is involved:
A resistor grounded on both ends is removed from the netlist hence, it shows no "plot my current" arrow when pointed at.
A resistor grounded on one end with the other end unconnected or connected to an open wire, is also removed from the netlist.
Neither resistor's current nor the open net's voltage can be plotted.
?
I tried a simple flat schematic containing a voltage source, V1 and two resistors, R1, R2. (I'm using 24.0.12)
?
If R2 is a resistor grounded on both ends, it remains in the net list, but is connected to 0 at both ends.
I(R2) cannot be plotted, and both ends of R2 report "This is ground".
?
V1 VCC 0 1
R1 VCC 0 1
R2 0 0 1
.tran 1
.backanno
.end
?
If R2 is a resistor grounded one end and open wire on the other, it remains in the net list, but is connected to 0 at one end and a unique net name on the other. I(R2) can be plotted, but it will be 0nA.
?
V1 VCC 0 1
R1 VCC 0 1
R2 0 N001 1
.tran 1
.backanno
.end
?
If R2 is a resistor grounded one end and open on the other, it remains in the net list, but is connected to 0 at one end, and a no-connection name "NC_01" on the other. I(R2) can be plotted, but it will be 0nA.
?
V1 VCC 0 1
R1 VCC 0 1
R2 0 NC_01 1
.tran 1
.backanno
.end
?
But it all cases, resistor R2 remains in the net list.
Can you provide a simple example that demonstrates why you to have to run the sim multiple times?
?
|
I have a very large PWM controlled Power Supply Circuit with dual outputs and It has been working fine until I added some new circuits as loads.? Since it takes a long time to reach steady-state operation, I usually simulate with some part value changes that allow it to come up faster.? Then, I use SAVEBIAS to create a file, that is used with UIC and LOADBIAS to kick-start the simulation for the correct value components, changes in loads, etc.
?
Recently, when I the file is ised with LOADBIAS it seems to use the file, but when I look at the Output file, it says, "Error: .nodeset syntax error."? I did not do anything with the file and used it exactly as SAVEBIAS created it.? I have a lot of Matrix Singularity issues with lots of nodes and wonder, if it is because the LOADBIAS is using some of the file and not all of it?
?
I looked in the discussions and only found something from a much earlier version of LTSPICE.? Something about incorrect use of the "#" sign in the file.
?
Any thoughts?
?
Thanks!
?
-BobT
|
Re: Any Good Reason to Create a Hierarchical Connector and Conductors to Route (Plumb) Ground Out of a Hierarchical Schematic
Hello All:
?
Who desires to have to run a long simulation twice because the software maker could/would not make sub-circuit probing work correctly on the first run?
?
Also, something else that may be unnoticed, since it also is not detailed in the help file.
Closing a sub-circuit window destroys your hard won gains from running that long simulation twice.
Re-opening that sub-circuit puts you right back to square one.
The net returns to saying "This is Ground." and the simulation must me run a third time to fix it again.
?
Sent:?Friday, February 07, 2025 at 8:32 PM
From:?"Andy I via groups.io" <AI.egrps+io@...>
To:[email protected]
Subject:?Re: [LTspice] Any Good Reason to Create a Hierarchical Connector and Conductors to Route (Plumb) Ground Out of a Hierarchical Schematic
On Fri, Feb 7, 2025 at 07:42 PM, eewiz wrote:
An explanation of that undesirable nature of LTspice could be added to the help file.
I am puzzled why you think it is "undesirable".
?
Andy
?
?
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eewiz
Tony Casey
John Woodgate