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<rd.weaver@n...> wrote: wrote: used complex found problems beginning. Hello Russell and Mike, thanks for your advices to solve

Helmut, The tolerances that are typically most useful to loosen are abstol, vntol, and chgtol. If you loosen reltol, it's best not to loosed it too much. The "No Bypass" check box is also often an

Reiner, I got the same or similar error message, when I tried to simulate a square-root circuit model. Of course, it is a big different between applications, but maybe good to know, why happened it.

<helmutsennewald@y...>" <helmutsennewald@y...> wrote: about

<helmutsennewald@y...>" <helmutsennewald@y...> wrote:

Hello Mike, Rainer could reduce the tolerances for the simulator in the Control Panel -

<helmutsennewald@y...>" <helmutsennewald@y...> wrote: help somewhere. Hello Bunny, my last sentence could be misleading . "No" refers to "Is the circuit ok ...". There is always hope! Best Regards,

<bunnyblues2001@y...>" <bunnyblues2001@y...> wrote: saved Hello Bunny, I downloaded this library directly from Teccor. http://www.teccor.com/asp/sitemap.asp?group=downloads Click on "SIDAC" and

Mike, thanks, for the quick answer! I played a little around and I was able to complete simulate the circuit. The wave-results are not as I wanted and I think I need a lot more simulations until my

I have no experience with Spice and what I know comes from the help file and the previous posts. I guess we all have to start somewhere. What I wanted to do was call up a model from a sidac library

Thanks again to Helmut and Peter. My digital design works now very well, with "real world" parameters. Christian

Rainer, It means the solver failed to converge for the circuit. Usually you have to change some aspect of the circuit to get it to run right. The 1533 is pretty complicated since it controls the slew

Hallo, I'm using scad3 for a few weeks and I'm very happy about the power and speed of simulation. Now, I tried a more complex simualtion with a LT1533 (I modified the sample) and got the following

--- In LTspice@..., "Helmut Sennewald <helmutsennewald@y...>" <helmutsennewald@y...> wrote: Sorry, I forgot the test circuit file. Helmut My test circuit(lv_4051.cir).

<sahawley@m...> wrote: it functional Hello, unfortunately I don't know any other source of SPICE model for this part. The behaviour looked indeed strange. It was ok with static driven control input,

I was looking around for a model of a low voltage MUX like the 74lv4051. I found a a 6 pin fragment in the Philips LV library (http://www.philipslogic.com/support/spice/) called SWI1. I wired it up

Hello Mike, thank you very much for the work on solving the .lib problem in

Please, change in the schematic CD4093.asc and symbol CD4093.asy node name gnd to G. It is universal, you can shift the level of the "GND" node. Peter

Hi Neil /New user: how to edit digital models? ----------------------------------------------- Try these: CD4093.asc ------------------------------------------------ Version 4 SHEET 1 892 692 WIRE 288

<neel_c@c...> wrote: is, Hello Christian, I forgot a very important detail. You have to specify some delay Td for every flipflop. All my simulated counters and flipflops have run as expected only when