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the You can use the standard resistor and capacitors model statements. It should be able to understand both Berkeley and PSpice syntax. (diode,resistor,capacitor...)? Absolutely not, but there isn't

Hi everybody, I am a new user of LTSpice. Looking into the model list I am not able to find the models for a semiconducor (diffused) resistors and capacitors. They are not very important but some

Try http://www.ee.bgu.ac.il/~pel/pdf-files/conf69.pdf Their may be something there you can use. Regards Brian -- Brian Howie | Tel: 0131 343 5590 BAE SYSTEMS | Fax: 0131 343 5050 Sensor Systems

<helmutsennewald@y...>" <helmutsennewald@y...> wrote:

<bunnyblues2001@y...>" <bunnyblues2001@y...> wrote: comes Hello, are you referencing this model? http://www.intusoft.com/nl50.htm#SPARK%20GAP%20MODELING It contains lines with non LTSpice syntax.

I need a model for a gas discharge tube similar to the Siemens A81- C90X, if anyone can help I'd appreciate it. I have just started to use LTSpice and would like to know if there is any information

I put up a version today(2.00t) that enables nested subcircuit definitions. Initial tests suggest the parameter passing is properly scoped. Please report any problems or crashes as soon as you detect

<brian.howie@b...> wrote: random

rand and white on their own are no use -these are rectangular random variables. Use a behavioural voltage source with V for example V=SQRT(-2*LN(white(time*1.07G)+0.5))*COS(2*PI*(white

Oh, yes. That is awkward. I'll see if I can't improve on this. The situation comes about historically because while the academic codes often do allow nested subcircuit definitions, the commercial

seems Hello Ron, a few minutes ago I sent Mike Engelhardt this question and asked him to answer into this thread at the YAHOO-LTSpice group. Best Regards Helmut

<helmutsennewald@y...>" <helmutsennewald@y...> wrote:

Hello Mike, thanks for the tip with the nested subcircuit. I had the chance to get the circuit files from Ron and remembering your advice, I immediatly looked into the LTSpice netlist. It was exactly

The error message occurs when the schematic resloves to netlist something like this: .subckt N1 N2 N3 name1 .subckt N4 N5 N6 name2 [...] .ends name2 .ends name1 The definition of name2 is inside

I created a symbol to represent a schematic (symbol saved as "block" (.asy)). When I placed it in a higher level schematic and tried to run a sim, I got an error message telling me that subcircuits

<sahawley@m...> wrote: Hello, there are two chances for your opamp models. The first one is creating a symbol for every opamp type you want to use. I think this is described in the LTSpice help pages.

Dear Mr. Sennewald, Thank you very much! You gave the final hint to solve the problem! And I already believed in a bug... As you said, there is no semiconductor device in my circuit. In fact, what you

<ingod@y...> wrote: Hello Ingo, there is a very easy way to make such a noise source. Firstly we should be aware that the rand() funktion has equal probability for every voltage level between 0 and 1.

discovered that whatever it is, my circuit works well, but with the > STEP command I get the error : Hello Bernhard, Cjo is normally a parameter of a semiconductor device. It seems you have any such

Hello, After a re-install of my system, I downloaded the newest edition of LTSpice. Now I tried out to simulate a simple circuit, and I discovered that whatever it is, my circuit works well, but with