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eetech00, That is pretty much all correct -- but I want to clarify what you wrote at the end.? I want to make sure that it is not taken out of context. The first line of a SPICE netlist file is

On Mon, Jul 3, 2023 at 11:05 AM, Andy I wrote: > > I think that the colors (and to some degree the file formatting) that > LTspice uses in its Netlist Editor do not distinguish between a full >

Some suggestions: C4 N001 batt1 1000p Rpar=0.1?? <-Rpar replaces resistor C5 N002 N001 10u Rpar=0.1????? <-Rpar replaces resistor C6 vsoc1 0 6480 Rpar=10k???????? <-Rpar replaces

I think that the colors (and to some degree the file formatting) that LTspice uses in its Netlist Editor do not distinguish between a full (top-level) SPICE Netlist, and something you're creating to

ADI responded here: https://ez.analog.com/design-tools-and-calculators/ltspice/f/q-a/571284/unexpected-line-length-limit-for-b-source/498078 . I don't think the answer works, but it triggered a nice

Well, caveat: it took at least 5 minutes, “Expanding PWL file”, before starting the simulation! Sent: Monday, July 03, 2023 9:36 AM To: [email protected] Subject: EXTERNAL: Re: [LTspice] Scaling a

Uploaded an amended schematic </g/LTspice/files/Temp/Li_Ion_Master_24V_ATC.zip> with a crude fix to clamp SOC between 0 and 1. -- Regards, Tony

Great suggestion! -- Regards, Tony

Sorry for a little confusion! I resaved the PWL file as a .csv so it could be edited in Excel. Your definition would be: PWL repeat forever (file=Test_PWL_2mod.txt) endrepeat Dave Sent: Monday, July

I fixed the 24V battery SOC table and amended the analysis duration to stop just after SOC reaches zero. The schematic has logical fault in it, so SOC is allowed to go outside the range 0 to 1, which

One suggestion I would make, aside from any corrections others may have: Your 38,000 second long PWL file can be reduced to the first 13 lines. The rest of the file is 18999 repeats of the same

On 03/07/2023 16:56, apotorski@... wrote: > I have been given the task of scaling down a 50V lithium ion battery to 24V. I think I have successfully uploaded both schematics and the PWL file in

I have been given the task of scaling down a 50V lithium ion battery to 24V. I think I have successfully uploaded both schematics and the PWL file in a zip file. The 50V schematic seems to work fine,

I uploaded a new file labeled Paschens-spark_gap. It's a work in progress. And thank you for your help Tony.

I mean: it always places a comment on the first line (the sub-schematic name) -- Regards, Tony

It's interesting that LTspice text editor still tries to nudge you to have a line above the .subckt definition. The syntax highlighting colour is always green (comment) for the first line, even if

Tony wrote, "It is also normal to begin a .subckt definition with a comment, starting with "*". Originally, SPICE assumed the first line was always a comment, but I'm not sure how strictly that is

Richard, For some reason, you don't seem to like following advice.? Where is your schematic (.asc) file where this error happened?? Where is the symbol (.asy) file?? I really don't care that

This is what you uploaded: .subckt sparkgap p n * Parameters * d: Gap distance in meters * aa: Gap area in sqr meters * p: Gas pressure in Pascals * Model constants ?.param A = 5.19e-11 ?.param B =

Yes, I looked at all the spark gap models and none were satisfactory to my needs.