Maybe a resistor across etch diode, but I think it is not necessary, the leakage current is big enough to balance the voltage across the diodes. Have used about 100,000 diode without resistor and not a single diode failed because of the voltage across them. The VR37 is big and expensive and sometimes hard to come by.

If you open op a TV20 (20KV) diode there is also not a resistor across each diode

While following this thread, it just dawned on me that I do not know
how to measure 3 phase power.? Any suggestions how to do this in real
life and ofcourse in LTspice as well.
?

开云体育

开云体育

Hello John

I wish the wealth of information that can be found over the Internet could let me know about the exact nature of the problem LTspice shows for this particular schematic.

> It might be helpful if you describe in detail the discrete

> digital structure that you are trying to simulate.

Thinking of sparing you all of possible errors from my English I uploaded CIC.asc in Temp. It may still be there, I haven't checked.?

> I have always found it challenging to translate discrete digital

> filters back into the analog for simulation.

> Perhaps the problem is that the analog nature of the delay lines

> allows small errors to grow due to the very high gain

So then part of the suspicion is true, LTspice is dedicated to analog simulation, despite all the efforts. It still is strange that using Filter with a 4 times interpolator, N=256 FIR will show no such odditites as CIC does, no matter how long the simulation. But it's also true that the CIC uses integrators while the FIR uses no feedback.

> Maybe buffering the output with quantizing b-source would help

> (one that can only take on valid digital values)

I'll try using int() to force some would-be quantizing, but later. For now a break. Thank you all for the advises and a Merry Christmas.

Vlad

Thank you for the directions, but I wouldn't have started something if I didn't have at least one clue about it :-)

Thank you for the directions, but I wouldn't have started something if I didn't have at least one clue about it :-) It's true that I can't say I'm an "expert", but I'll manage, somehow. The problem, though, isn't knowing what a CIC does, but what LTspice shows up when using it, otherwise I wouldn't have asked for help here.

Vlad

I really don't know what a CIC filter is and how it is supposed to

work.


If you say so. Being no expert either (by far), here's what I know, in short: they're a cheaper approach to interpolators/decimators because they're multiplier-free (not that it would matter in LTspice) and can have arbitrary rates.

> I really don't know what a CIC filter is and how it is supposed to work.

If you say so. Being no expert either (by far), here's what I know, in short: they're a cheaper approach to interpolators/decimators because they're multiplier-free (not that it would matter in LTspice) and can have arbitrary rates. The lower chain are the integrators, as you said: y[n]=y[n-1]+x[n] (hence the inverting tline fed to the inverting input of the G-source). Due to the high gain at DC they're the most unstable and a CIC of N sections will have a gain at the output (M*R)**N (the inverse of the current input gain), where R is the rate and M the number of samples for the comb section (y[n]=x[n]-x[n-M]). This is also one of the major downsides, the bit growth. Inverting the chain order and using downsampler results in a decimator.

Now, as far as LTspice is concerned, considering two adjacent samples as a step input, and since a tline will not interpret this as a digital signal (well, nothing, really) it means that the sharp shape will not be preserved, anymore. Because of this, I would expect the signal to be distorted after 8 stages of integrators, but only around the step change. As you noted, even if you have to zoom in quite a bit to realize that, the waveshape is no longer a "straight line" and, because we're talking about integrators, the smallest error will gain large proportions at the end.

So, let's say that this is the normal behaviour, that passing a (sampled) signal through several tline stages will distort the signal up until the samples, themselves, no more "straight line". But then how come this problem doesn't arise in the FIR filter? If you try Files/Filter/Filter/Filter.* and set it to a 256 length FIR and similar settings as the CIC, you'll notice no such problem. True, you may need to tinker with tr and td, but even the last sample in the simulation will be "normal", LTspice-wise.

As mentioned, I also tried adding S&H between stages. After all, the delay is a S&H in itself. At first, between 6th and 7th as there seemed to be where the errors gained proportions (later ending up with one between every stage). Like this, the output goes well sampled for a while, but then starts going exponentially upwards or downwards because of the "non-linearity" of the samples, the wobbly waveform, they sample with errors and all. I thought this is because of the upsampler. The SW has Ron=1 and Roff=1u, meaning that where there should be zero-samples there are, in fact, non-zero ones, a million times lower, yes, but non-zero. So, I replaced the SW with R17 and added a B-source with V(0.3) [upsampler clock] times V(108) [the output of the 8th comb]. Since the clock has 0 and 1V values only, the zero-samples were as they should be. Not only that didn't solve the problem, but it only brought another one as the B-source itself needed tripdv/tripdt settings on its own, which meant an extra complication because tinkering with those two settings implies first running the simulation, then modifying, then re-running, ...

In the end, the only ones (hard-)influencing the result are the clocks made with voltage/current sources. For this reason, the S&H, as it is now, has a sine source as its clock, to avoid sharp transitions and let only V(0.3), the rate clock, to affect the sampling. The analog input signal, V1, also influences this; try changing it, for example, to: pulse 0 3 0 {0.77/f} {0.23/f} 0 {1/f} and see the what happens.?

If you have a bit of time and are willing, see for yourself with this little experiment: set up one integrator just like those in the CIC, with Td=1, and use this input:

V1 0 a pulse 0 1 1 1m 1m {ton} 2

Run this for 10 sec, no timestep imposed, with ton=0.5 and then ton=1, see the difference. Also relevant is using the source as simply: pulse 0 1 1 1m , same simulation. It can be clearly seen that, as long as there are no "synced" sharp transitions from the source, the output of the integrator simply relaxes itself greatly. If it would have been only this, fine by me, a tight timestep should solve the problem, but the tline seems to count that relaxed timestep as its input. Adding a simple inverter, separated, with output connected to input and td=1 (oscillator) won't solve the problem, its tripdt only influences the A-device. Adding a B-source (between ground and x) with delay(V(a),1) will influence the general result if tripdv/tripdt are specified, but that's not a solution because, like above, those two settings imply running and re-running the simulation when this is meant to be a subcircuit.

At this point, I honestly don't know whether this should be the answer to expect or not, to expect those spikes to happen or not. I'm also out of ideas at this point.

Vlad

Use UF4007(SF4007), they are 1A, 1000V, 75nS Trr and cheap. 1n4148 have only 75volt reveres voltage.

10pcs. in series gives 10KV. I would use 11 to have som margen.