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Also i need to find a potiometer spice and symbol that works.

Also check the group messages from the last 48 hours.

Andy

above 10 nS step not working!!!

Did you fix the power supply voltages, the input amplitude, and the edge
rate?

--- In LTspice@..., "Helmut" <helmutsennewald@...> wrote:

Hello,

I want only remind that Mike is on tour in Australia this week.






Best regards,
Helmut

This has been asked before, but it would be great if some of these events could be recorded and put on youtube or dailymotion or similar.

Thanks Helmut!!

I insert this param in my modelling

.options cshunt=1e-16
.options ptrantau=.1u
.tran 0 7ms 5ms 10ns

above 10 nS step not working!!!

i sad (((((( modelling very slowly

--- In LTspice@..., John Woodgate <jmw@...> wrote:

AVG reported a 'Java obfuscation' malware threat on that page.

John, perhaps you meant well, but it is irresponsible of you to
smear this website without first doing some basic substantiating
research to support what in all likelihood was a false alarm that
AVG generated.

After looking a bit on the web I could find nothing to support
your warnings about what by all indications is a perfectly safe
technical website/forum. What I did find directly contradicts
your scare message. For example, these services give Designers-
Guide.org a completely SAFE rating:





Please be more careful in future. -- a.s.

In message <kt0lfh+f4cd@...>, dated Sat, 27 Jul 2013, analogspiceman <analogspiceman@...> writes:

I also have downloaded the node-limited free trial version of SIMPLIS and have compared its abilities to LTspice. SIMPLIS is amazingly powerful and very impressive. I hope Mike takes notice and adds some similar capabilities and features to LTspice. See:

AVG reported a 'Java obfuscation' malware threat on that page.
--
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Why is the stapler always empty just when you want it?

John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK

--- In LTspice@..., analogspiceman wrote:

Frank Wiedmann alerted me to a thread on the Designers-Guide.org
circuit simulation forum where a user was trying to use SIMPLIS to
obtain the frequency response of a boost converter. Frank asked
me to comment about the "folded" shape of the SIMPLIS generated
loopgain that was not expected by the original poster. In the
thread I have uploaded analysis results for the same circuit
simulated in LTspice.

I also have downloaded the node-limited free trial version of
SIMPLIS and have compared its abilities to LTspice. SIMPLIS is
amazingly powerful and very impressive. I hope Mike takes notice
and adds some similar capabilities and features to LTspice. See:

A lot of simulators have added POP/PSS (Periodic Operating Point/
Periodic Steady-State) solvers to their repertoire. Micro-Cap
recently added POP capability. They discuss it here:



Notice the effect it has on the resolution of the FFT example.

Many other simulators take this further with the addition of a
time domain based fast running FRA (Frequency Response Analyzer)
capability (SIMPLIS, PSIM and NL5 come to mind, but there are
others as well). This capability allows the simulator to directly
produce Bode plots and loop gain analyses for switched circuits
such as switched-mode power supplies (a very good feature, IMO).

The application of small-signal frequency-domain analysis to
switching piecewise-linear systems presents tremendous challenges.
Some years ago I made a FRA completely within LTspice using its
special a-devices (still available in our group files section).
About that time, Mike added some FRA examples to LTspice that use
post processing (.meas statements) to complete the analysis and
plot the results. Mike writes about this at length in the FAQ
section of LTspice's Help file topic ("How to get a Bode Plot
from a SMPS"). He argues that it is not worth the trouble because
it is generally not needed in order to be able to compensate a
design using an LTC IC because most of them use current mode
control.

Both of the above LTspice FRA approaches (mine and Mike's) are
painfully slow and suffer numerical dynamic range noise problems.
SIMPLIS (which has a free, but node limited demo) will solve for
the frequency response and/or loop gain of SMPS circuits with no
noise issues and will run the complete response analysis within a
few minutes (LTspice might take hours to do the same thing).

Here is link to a paper in which a basic buck stage is simulated
with SIMPLIS. The schematic is on page 16 and the SIMPLIS output
is shown on the next page (out to several times the switching
frequency).



The results shown look very clean with just the right sort of loop
response as expected for the extended frequency range simulated.
In the past, I have measured SMPS loops with an HP4194A loop gain
analyzer. The lab measurements look just like the SIMPLIS results.
I have also used the Ridley AP analyzer, but it is not quite as
accurate as the HP4194A. I have been told that the Venable analyzer
produces very good results as well (perhaps the best of all).

SIMPLIS type simulators are very fast in part because they approx-
imate all the nonlinear switched devices (diode, MOSFETs, etc.)
with line segment approximations through the switch transition
(some allow the number of segments used to be specified). Part of
their speed comes from the use of the POP/PSS analysis to quickly
find the operating point. I think a large part of their speed
also comes from having a native frequency response analyzer device
directly built into the simulator code.

LTspice already has a lot of these types of capabilities (ideal
diodes and switches with smooth transitions), POP/PSS sensing (but
no accelerator to get there). It has fast state transition sensing
devices (the digital a-devices). Personally, I would like to see
Mike add a native FRA device to LTspice so that it could generate
Bode plot loop-gain curves for switched mode products. It would
not be necessary to be as fast as SIMPLIS because LTspice does not
use the less accurate line segment approximations, but noise free
results would be a must. Run times of one third to one tenth the
speed of SIMPLIS (or the others) would be okay.

There are lots of tricks Mike could use to speed up the analysis.
For example, the Venable analyzer looks at phase change rate to
dynamically adjust the spacing of the frequency measurement points.

For LTC current mode ICs, all this may not be necessary, but for
general SMPS design there are many cases in which second order
effects dominate the loop response (series ESR in capacitors,
parallel loss in inductors, variable operating point dependent
delays in opto-isolator devices, etc.). In cases like these, or
when using non standard control methods, depending on averaged
models and standard concepts may lead to false conclusions and
bad choices in compensation design. A time domain FRA capability
in an excellent general purpose simulator such as is LTspice would
allow the designer better insight into the circuit and would be a
big plus to its feature set.

--- In LTspice@..., legg@... wrote:

A TEK scope plot of two waveforms, exported as a single CSV file.
Do you simply strip them, to separate columns and process as two PWL files?

Recall doing it before, a few years ago, but damned if I can recall how.

RL

There was a title row....That's fixed.

Negative time? I'll just bodge it with a formula row.

RL

A TEK scope plot of two waveforms, exported as a single CSV file.
Do you simply strip them, to separate columns and process as two PWL files?

Recall doing it before, a few years ago, but damned if I can recall how.

RL

Hello!

I tried to simulate a +9...+30 Vin, +3.5...+4.2 Vout dc/dc converter using LTC3765 & 66 chips.
While it simulates nice using default LT settings as in jigs directory,
any attempt to use lower input voltage in the area +9..12 Vin failed due to abnormal Ndrv pin behaviour.
After several milliseconds of proper work it simply stops feeding Vcc pin through mosfet.

Why it makes this "brownout" ?

--- In LTspice@..., "cory991" <cory991@...> wrote:

Can anyone tell me where to find a schematic for the arduino pulser.
Also i need to find a potiometer spice and symbol that works.


Thanks

I'm not really sure if LTspice would be the best program for you.
Arduino is a programmable microcontroller and requires programming before it will do anything.
Search on google for "fritzing". Fritzing is a breadboard and pcb program with Arduino templates.

If you look through the files and examples and index on this site you will find a potentiometer model and symbol created by our moderator that works.

--- In LTspice@..., "desi2209" <desi0985@...> wrote:

i'm working with power line communication systems.
The articles explain the trasmission line theory for cable modelling, but then start to talk about abcd matrix and the advantage to describe the cable with this element, because on power line cable there are several branches and a complex topology to describe and the abcd matrix permitts to evaluate the total transfer function simply with matrix multiplications.

What i need is a way to define different elements of the line (segment of cable, different types of branches) in order to have a database to use to display the desired network topology and analyze the signal behaviour through the line.

Let me save you a lot a trouble. The domestic ring main is not a high speed data circuit. If you take data at 1Mbps then 1 data bit is just 1 micro second duration.
This is very short compared to any electrical spikes, surges, or noise on a domestic ring main. It's also the reason why powerlines are inferior to ethernet or wireless. I've seen very poor and erratic throughputs on power line adapters always ending up loosing be50 and 90% of the original speed.
Don't let this put you off, but you will need to explain in your simulation how the power line overcomes data dropouts, e.g. 25ms contact bounce from a switch and even longer noise periods from heavy loads like kettles or devices containing motors.

Can anyone tell me where to find a schematic for the arduino pulser.
Also i need to find a potiometer spice and symbol that works.


Thanks

His model seems to run OK (on my computer) as long as it stays below
slew-rate limiting.

As soon as the output slew rate hits +/-10V/us and starts flattening out,
that's when it starts getting the "time step too small" errors.

Andy

Hello,

You can ignore the warnings about "Length shorter ...".

All the Microchip opamp models make a lot of trouble with
convergence problems in LTspice. Sometimes I can find a solution,
sometimes not.

I have uploaded an example with the MCP631.

Files > Lib > MCP631_test.zip.

It required at least these two options.

.options cshunt=1e-16
.options ptrantau=.1u

Best regards,
Helmut

Instance "m:u1:14": Length shorter than recommended for a level 1 MOSFET.
Instance "m:u1:12": Length shorter than recommended for a level 1 MOSFET.

Those are just warnings. I see those a lot. Level 1 MOSFETs were around
in 1973 when SPICE was brand new, and MOS channel lengths as small as a
micron were uncommon. Microchip's models have 2 micron channel lengths.
But that's Microchip's problem, for using a Level 1 transistor model where
they probably shouldn't be using one.

Most of the remaining messages in your log file are status messages and can
be ignored, until here:

Heightened Def Con from 1.32884e-008

++++++++++++++++++++++++++++++++++++++++++++++++++

Fatal Error: Analysis: Time step too small; time = 1.32884e-008, timestep

= 1.25e-019: trouble with node "u1:30"

This is where LTspice runs into trouble. I think the reason is a
combination of the large supply voltages, an input amplitude that pushes
the op-amp into saturation, and fast edge rates.

On the spec sheet, the small-signal step response rise time is 20ns
typical, and the large-signal slew rate limit is 10V/us. If the op-amp had
worked linearly with your voltages, the output slew rate would have been
50V/us, well beyond what the op-amp is capable of.

Andy

Please leave schematic files as files, and upload them to the Temp folder.
Pasting them into an email makes for extra tedious work.

Your simulation severely over-stresses the op-amp. Its absolute maximum
power supply (Vdd-Vss) is 6.5V, with 5.5V being the recommended maximum.
Here you have applied 30V. That would surely fry the real op-amp.

The input amplitude also needs to be reduced, to keep the output from
saturating. Try setting it to 0.1V instead of 1.0V.

The simulation does seem to have difficulty if the amplitude is increased,
along with the 100ns rise and fall times (generating "timestep too small"
errors). Try backing them off to 1us rise and fall times and then the
amplitude can be increased. Perhaps the model doesn't like very fast input
slew rates.

Andy

Instance "m:u1:14": Length shorter than recommended for a level 1 MOSFET.
Instance "m:u1:12": Length shorter than recommended for a level 1 MOSFET.
Direct Newton iteration failed to find .op point. (Use ".option noopiter" to skip.)
Starting Gmin stepping
Increasing initial diagonal Gmin to 100
Increasing initial diagonal Gmin to 1000
Increasing initial diagonal Gmin to 10000
Increasing initial diagonal Gmin to 100000
Gmin = 100000
Gmin = 10737.4
Gmin = 1152.92
Gmin = 123.794
Gmin = 13.2923
Gmin = 1.42725
vernier = 0.5
vernier = 0.25
vernier = 0.125
vernier = 0.0625
Gmin = 1.32263
vernier = 0.03125
vernier = 0.015625
vernier = 0.0078125
vernier = 0.00390625
Gmin = 1.30727
vernier = 0.00195313
vernier = 0.00260417
Gmin = 1.30154
vernier = 0.00347222
vernier = 0.00462963
Gmin = 1.29076
vernier = 0.00617283
Gmin = 1.27346
vernier = 0.00823044
vernier = 0.0109739
Gmin = 1.24563
vernier = 0.0146319
vernier = 0.0195092
Gmin = 1.2028
vernier = 0.0260122
Gmin = 1.13645
vernier = 0.034683
vernier = 0.046244
Gmin = 1.03577
vernier = 0.0616586
vernier = 0.0822114
Gmin = 0.894523
vernier = 0.109615
Gmin = 0.705843
vernier = 0.146154
vernier = 0.194871
Gmin = 0.480262
vernier = 0.259828
vernier = 0.346438
Gmin = 0.262686
vernier = 0.461917
Gmin = 0.100406
vernier = 0.615889
vernier = 0.821185
Gmin = 0.0217694
vernier = 1
vernier = 0.5
vernier = 0.25
Gmin = 0.00509242
vernier = 0.125
vernier = 0.0625
vernier = 0.03125
vernier = 0.015625
vernier = 0.0078125
vernier = 0.00390625
vernier = 0.00195313
vernier = 0.000976563
vernier = 0.000488281
Gmin = 0
Gmin = 0
Gmin stepping failed

Starting source stepping with srcstepmethod=0
Source Step = 3.0303%
Source Step = 33.3333%
Source Step = 63.6364%
Source Step = 93.9394%
Source stepping succeeded in finding the operating point.

Heightened Def Con from 1.32884e-008 ++++++++++++++++++++++++++++++++++++++++++++++++++Fatal Error: Analysis: Time step too small; time = 1.32884e-008, timestep = 1.25e-019: trouble with node "u1:30"

test_mcp6xx.asc

Version 4
SHEET 1 880 708
WIRE -128 -16 -192 -16
WIRE -16 -16 -48 -16
WIRE 48 -16 -16 -16
WIRE 208 -16 128 -16
WIRE -192 16 -192 -16
WIRE 112 112 112 96
WIRE -16 128 -16 -16
WIRE 80 128 -16 128
WIRE 208 144 208 -16
WIRE 208 144 144 144
WIRE 272 144 208 144
WIRE -128 160 -192 160
WIRE 80 160 -48 160
WIRE -480 192 -480 176
WIRE -352 192 -352 176
WIRE -192 192 -192 160
WIRE 112 208 112 176
WIRE -480 288 -480 272
WIRE -352 288 -352 272
WIRE -192 288 -192 272
FLAG 112 96 VCC
FLAG 112 208 VSS
FLAG -192 288 0
FLAG -480 288 0
FLAG -352 288 0
FLAG -480 176 VCC
FLAG -352 176 VSS
FLAG -192 16 0
FLAG 272 144 out
IOPIN 272 144 Out
FLAG -192 160 in
SYMBOL voltage -192 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 .1u .1u 9.9u 20u)
SYMBOL voltage -480 176 R0
SYMATTR InstName V2
SYMATTR Value +15V
SYMBOL voltage -352 176 R0
SYMATTR InstName V3
SYMATTR Value -15V
SYMBOL res 32 0 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL res -144 0 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 2.5k
SYMBOL res -144 176 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL MCP63X 112 144 R0
SYMATTR InstName U1
TEXT -472 -128 Left 2 !.tran 40u
TEXT -472 -96 Left 2 !.options plotwinsize=0

Here is a bit of netlist code that uses the part. Almost everyone here
prefers a schematic (.asc), but plain netlists work too.

Vdd Vdd 0 2.5V
Vss Vss 0 -2.5V
Vsig sig 0 sine (0V 1V 1kHz) AC 1V
Rin sig inp 1k
Rfb out inn 5k
Rg inn 0 5k
X1 inp inn vdd vss out mcp63x
.tran 100ms
*.ac dec 10 1Hz 100MEGHz

And of course you need a Title line and an .END line, and your model.

Andy