Re: Flip Flop and NAND gate
On Tue, May 27, 2025 at 09:21 AM, <guilhermesouzam01@...> wrote:
Hello All!
?
I¡¯m trying to create an SR flip-flop circuit with a clock in LTspice. To do this, I¡¯m using the AND logic gate available under Component/Digital. I¡¯m assuming it provides two output options: normal and inverted. Therefore, I¡¯m using the inverted output to form a NAND gate.
However, it¡¯s not working. My Q output doesn¡¯t match the truth table of this flip-flop.
Could someone guide me? I¡¯ve never created a digital circuit in LTspice before.
I¡¯ve attached the FlipFlop_SR_Clock circuit in Temp.
Thank you!
I've uploaded a corrected version.
FlipFlop_SR_Clock_eT.zip
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Also posted a photo
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Re: TL074 model in 24.1.8
I hope we will soon get a long-term stable
version, not too many versions ahead.
On 2025-05-27 21:16, eetech00 via
groups.io wrote:
On Tue, May 27, 2025 at 11:13 AM, Hawker wrote:
Worked in 24.0.x, does not work in 24.1.8
Works fine in 24.1.9
?
eT
--
Best wishes John Woodgate RAYLEIGH Essex OOO-Own Opinions Only
If something is true: * as far as we know - it's science *for
certain - it's mathematics *unquestionably - it's religion
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Re: TL074 model in 24.1.8
On Tue, May 27, 2025 at 11:13 AM, Hawker wrote:
Worked in 24.0.x, does not work in 24.1.8
Works fine in 24.1.9
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eT
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Re: TL074 model in 24.1.8
Looks like the problem is not about what's inside the model.
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The error message is cryptic, but suggests something like a wrong file being called.
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Andy
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Re: Flip Flop and NAND gate
Clk doesn't need to cross 50% of Vcc.? Just needs to cross the ref input voltage of the A-devices, which is 0.5 V unless changed.
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Andy
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Re: Flip Flop and NAND gate
Until the first clock edge, the output is undefined, and just oscillates.
After all of the suggested fixes, the FF is toggling nicely, BUT
Clk is running at 100kHz, but Q is outputting a 0-5V triangle wave at 78MHz
?
Dave
?
?
also, I see you have a 5V clock signal, but are using 0/1 V levels for S and R signals. A-type elements (i.e., logic gates) default to 0/1 V logic levels.? Read about A-type elements in help. Finally, propagation delay is set with the Td
parameter.
?
add propagation delay to each digital logic element. then see what happens.
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Ok so y'all caught an ancient 5457 model bug, that worked non the less before 24.1.x. Can you tell me what is wrong with the ancient TI TL074 model that has worked (though limited) forever until now?
?
Worked in 24.0.x, does not work in 24.1.8
I have
.include TL074.301
Just like all the other models.
I get the error
C:\Users\{USER}\Documents\LTspiceXVII\lib\sub\TL074.301(43): Expected device instantiation or directive here.
^
All other TI included models so far work.
Model looks like this
* TL074 OPERATIONAL AMPLIFIER "MACROMODEL" SUBCIRCUIT
* CREATED USING PARTS RELEASE 4.01 ON 06/16/89 AT 13:08
* (REV N/A) ? ? ?SUPPLY VOLTAGE: +/-15V
* CONNECTIONS: ? NON-INVERTING INPUT
* ? ? ? ? ? ? ? ?| INVERTING INPUT
* ? ? ? ? ? ? ? ?| | POSITIVE POWER SUPPLY
* ? ? ? ? ? ? ? ?| | | NEGATIVE POWER SUPPLY
* ? ? ? ? ? ? ? ?| | | | OUTPUT
* ? ? ? ? ? ? ? ?| | | | |
.SUBCKT TL074 ? ?1 2 3 4 5
*
? C1 ? 11 12 3.498E-12
? C2 ? ?6 ?7 15.00E-12
? DC ? ?5 53 DX
? DE ? 54 ?5 DX
? DLP ?90 91 DX
? DLN ?92 90 DX
? DP ? ?4 ?3 DX
? EGND 99 ?0 POLY(2) (3,0) (4,0) 0 .5 .5
? FB ? ?7 99 POLY(5) VB VC VE VLP VLN 0 4.715E6 -5E6 5E6 5E6 -5E6
? GA ? ?6 ?0 11 12 282.8E-6
? GCM ? 0 ?6 10 99 8.942E-9
? ISS ? 3 10 DC 195.0E-6
? HLIM 90 ?0 VLIM 1K
? J1 ? 11 ?2 10 JX
? J2 ? 12 ?1 10 JX
? R2 ? ?6 ?9 100.0E3
? RD1 ? 4 11 3.536E3
? RD2 ? 4 12 3.536E3
? RO1 ? 8 ?5 150
? RO2 ? 7 99 150
? RP ? ?3 ?4 2.143E3
? RSS ?10 99 1.026E6
? VB ? ?9 ?0 DC 0
? VC ? ?3 53 DC 2.200
? VE ? 54 ?4 DC 2.200
? VLIM ?7 ?8 DC 0
? VLP ?91 ?0 DC 25
? VLN ? 0 92 DC 25
.MODEL DX D(IS=800.0E-18)
.MODEL JX PJF(IS=15.00E-12 BETA=270.1E-6 VTO=-1)
.ENDS
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Re: Flip Flop and NAND gate
NO difference, slightly surprisingly to me, because Clk never crosses 50% of Vcc
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toggle quoted message
Show quoted text
From: [email protected] <[email protected]>
On Behalf Of John Woodgate
Sent: Tuesday, May 27, 2025 10:51 AM
To: [email protected]
Subject: EXTERNAL: Re: [LTspice] Flip Flop and NAND gate
?
Try reducing the clock voltage to 1 volt.
On 2025-05-27 18:43, Bell, Dave via groups.io wrote:
After all of the suggested fixes, the FF is toggling nicely, BUT
Clk is running at 100kHz, but Q is outputting a 0-5V triangle wave at 78MHz
?
Dave
?
?
also, I see you have a 5V clock signal, but are using 0/1 V levels for S and R signals. A-type elements (i.e., logic gates) default to 0/1 V logic levels.? Read about A-type elements in help. Finally, propagation delay is set with the Td
parameter.
?
add propagation delay to each digital logic element. then see what happens.
--
Best wishes John Woodgate RAYLEIGH Essex OOO-Own Opinions Only If something is true: * as far as we know - it's science *for certain - it's mathematics *unquestionably - it's religion
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Re: Flip Flop and NAND gate
Try reducing the clock voltage to 1 volt.
On 2025-05-27 18:43, Bell, Dave via
groups.io wrote:
After all of
the suggested fixes, the FF is toggling nicely, BUT
Clk is
running at 100kHz, but Q is outputting a 0-5V triangle wave
at 78MHz
?
Dave
?
?
also, I see you have a 5V clock signal,
but are using 0/1 V levels for S and R signals. A-type
elements (i.e., logic gates) default to 0/1 V logic
levels.? Read about A-type elements in help. Finally,
propagation delay is set with the Td parameter.
?
add propagation delay to each digital
logic element. then see what happens.
--
Best wishes John Woodgate RAYLEIGH Essex OOO-Own Opinions Only
If something is true: * as far as we know - it's science *for
certain - it's mathematics *unquestionably - it's religion
|
Re: Flip Flop and NAND gate
After all of the suggested fixes, the FF is toggling nicely, BUT
Clk is running at 100kHz, but Q is outputting a 0-5V triangle wave at 78MHz
?
Dave
?
toggle quoted message
Show quoted text
From: [email protected] <[email protected]>
On Behalf Of Walter Sjursen via groups.io
Sent: Tuesday, May 27, 2025 9:53 AM
To: [email protected]
Subject: EXTERNAL: Re: [LTspice] Flip Flop and NAND gate
?
also, I see you have a 5V clock signal, but are using 0/1 V levels for S and R signals. A-type elements (i.e., logic gates) default to 0/1 V logic levels.? Read about A-type elements in help. Finally, propagation delay is set with the Td
parameter.
?
add propagation delay to each digital logic element. then see what happens.
|
Re: Flip Flop and NAND gate
also, I see you have a 5V clock signal, but are using 0/1 V levels for S and R signals. A-type elements (i.e., logic gates) default to 0/1 V logic levels.? Read about A-type elements in help. Finally, propagation delay is set with the Td parameter.
add propagation delay to each digital logic element. then see what happens.
|
Re: Flip Flop and NAND gate
On Tue, May 27, 2025 at 12:21 PM, <guilhermesouzam01@...> wrote:
However, it¡¯s not working. My Q output doesn¡¯t match the truth table of this flip-flop.
It looks to me like it's working.
?
You have applied a steady High to the S input, and a Low to the R input.? So the Q output is driven High and Q/ is driven Low.
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Show us your truth table that says something else.
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FYI, when building circuits like this using those Digital gates, especially ones with feedback like this, note that you really need to give some delay to some of them.? By default, each gate in the Digital library folder has zero propagation delay, and that can lead to race conditions.? Right-click on each gate and add this:
Td=10n
in the Value attribute line.
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I'm glad that you commented-out the command ".lib and.asy".? That line made no sense.? An .ASY file is a symbol; it is not a SPICE model and it would be deadly wrong to try to include it in the netlist for any simulation.
?
Andy
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Re: Flip Flop and NAND gate
add propagation delay to each digital logic element. then see what happens.
|
Hello All!
?
I¡¯m trying to create an SR flip-flop circuit with a clock in LTspice. To do this, I¡¯m using the AND logic gate available under Component/Digital. I¡¯m assuming it provides two output options: normal and inverted. Therefore, I¡¯m using the inverted output to form a NAND gate.
However, it¡¯s not working. My Q output doesn¡¯t match the truth table of this flip-flop.
Could someone guide me? I¡¯ve never created a digital circuit in LTspice before.
I¡¯ve attached the FlipFlop_SR_Clock circuit in Temp.
Thank you!
|
On Tue, May 27, 2025 at 10:27 AM, bwolfe58 wrote:
The first .MODEL statement is a single line of text but it is displayed as two lines in this response.
That depends on your browser's screen width.
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The root cause of the original problem apparently was because the .model line had an errant "+" sign in the middle of it, which should not be there.? My guess is that the .model began life as two lines (with the required "+" continuation character), and someone thought they would be clever by combining both lines, but they forgot to remove the "+" sign - thus introducing improper syntax.
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Andy
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The first .MODEL statement is a single line of text but it is displayed as two lines in this response.
The second .MODEL statement is two lines with the + sign beginning the second line as shown.
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On 27/05/2025 07:55, suded emmanuel via
groups.io wrote:
I just installed LTspice 24, I can use both old spice and
new, they both work!
I still need to auto generate the models used by old LTspice
(to build the symbols) to be able to use them in LTspice 24, is
there a way that I can use the models in the new LTspice 24 with
out regenerating please?
You are not very clear about what you have actually done.
Did you install LTspice 24 alongside your older existing version of
LTspice (presuming V17.x), or did you effectively perform an upgrade
over the top of your existing installation?
Or did you mean that old schematics created with your previous
version still work with the new version?
You are also not clear which version 24 you have just installed. I
presume you mean V24.1, since that is the latest one available on
ADI's website? (There are significant changes between 24.0 and
24.1.) Now we're at 24.1.8 (at the time of writing), most of the
initial issues arising have been addressed, but not all of them.
Whether you can use auto-generated symbols from your old version
depends whether they still exist. Did you back up the old libraries?
(BTW, you didn't auto-generate any models, it was the symbols you
auto-generated from the models. Or do I completely misunderstand
what you mean?) We can't know what you did unless you tell us. I
would advise anyway, that you get out of the habit of using
auto-generated symbols. There are several issues with them:
- They are hard-coded with your local machine's absolute path,
making sharing them problematic.
- They contain no information about the function
- They're ugly.
--
Regards,
Tony
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There should be no need to regenerate anything
if you mean LTspice's native models. Version 24.1.x uses the
same models and symbols as version 17.x.x, and adds many new
ones. If you have actually found a problem, please explain more
clearly about it. You could look at 'Program Updates' in the FAQ
in the Help.
On 2025-05-27 06:55, suded emmanuel via
groups.io wrote:
Hi,
I just installed LTspice 24, I can use both old spice and
new, they both work!
I still need to auto generate the models used by old LTspice
(to build the symbols) to be able to use them in LTspice 24, is
there a way that I can use the models in the new LTspice 24 with
out regenerating please?
Regards,
Suded
--
Best wishes John Woodgate RAYLEIGH Essex OOO-Own Opinions Only
If something is true: * as far as we know - it's science *for
certain - it's mathematics *unquestionably - it's religion
|
Hi,
I just installed LTspice 24, I can use both old spice and new, they both work!
I still need to auto generate the models used by old LTspice (to build the symbols) to be able to use them in LTspice 24, is there a way that I can use the models in the new LTspice 24 with out regenerating please?
Regards,
Suded
|
Bell, Dave
John Woodgate
Tony Casey