Re: Flip Flop and NAND gate
Try reducing the clock voltage to 1 volt.
On 2025-05-27 18:43, Bell, Dave via
groups.io wrote:
After all of
the suggested fixes, the FF is toggling nicely, BUT
Clk is
running at 100kHz, but Q is outputting a 0-5V triangle wave
at 78MHz
?
Dave
?
?
also, I see you have a 5V clock signal,
but are using 0/1 V levels for S and R signals. A-type
elements (i.e., logic gates) default to 0/1 V logic
levels.? Read about A-type elements in help. Finally,
propagation delay is set with the Td parameter.
?
add propagation delay to each digital
logic element. then see what happens.
--
Best wishes John Woodgate RAYLEIGH Essex OOO-Own Opinions Only
If something is true: * as far as we know - it's science *for
certain - it's mathematics *unquestionably - it's religion
|
Re: Flip Flop and NAND gate
After all of the suggested fixes, the FF is toggling nicely, BUT
Clk is running at 100kHz, but Q is outputting a 0-5V triangle wave at 78MHz
?
Dave
?
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From: [email protected] <[email protected]>
On Behalf Of Walter Sjursen via groups.io
Sent: Tuesday, May 27, 2025 9:53 AM
To: [email protected]
Subject: EXTERNAL: Re: [LTspice] Flip Flop and NAND gate
?
also, I see you have a 5V clock signal, but are using 0/1 V levels for S and R signals. A-type elements (i.e., logic gates) default to 0/1 V logic levels.? Read about A-type elements in help. Finally, propagation delay is set with the Td
parameter.
?
add propagation delay to each digital logic element. then see what happens.
|
Re: Flip Flop and NAND gate
also, I see you have a 5V clock signal, but are using 0/1 V levels for S and R signals. A-type elements (i.e., logic gates) default to 0/1 V logic levels.? Read about A-type elements in help. Finally, propagation delay is set with the Td parameter.
add propagation delay to each digital logic element. then see what happens.
|
Re: Flip Flop and NAND gate
On Tue, May 27, 2025 at 12:21 PM, <guilhermesouzam01@...> wrote:
However, it’s not working. My Q output doesn’t match the truth table of this flip-flop.
It looks to me like it's working.
?
You have applied a steady High to the S input, and a Low to the R input.? So the Q output is driven High and Q/ is driven Low.
?
Show us your truth table that says something else.
?
FYI, when building circuits like this using those Digital gates, especially ones with feedback like this, note that you really need to give some delay to some of them.? By default, each gate in the Digital library folder has zero propagation delay, and that can lead to race conditions.? Right-click on each gate and add this:
Td=10n
in the Value attribute line.
?
I'm glad that you commented-out the command ".lib and.asy".? That line made no sense.? An .ASY file is a symbol; it is not a SPICE model and it would be deadly wrong to try to include it in the netlist for any simulation.
?
Andy
?
|
Re: Flip Flop and NAND gate
add propagation delay to each digital logic element. then see what happens.
|
Hello All!
?
I’m trying to create an SR flip-flop circuit with a clock in LTspice. To do this, I’m using the AND logic gate available under Component/Digital. I’m assuming it provides two output options: normal and inverted. Therefore, I’m using the inverted output to form a NAND gate.
However, it’s not working. My Q output doesn’t match the truth table of this flip-flop.
Could someone guide me? I’ve never created a digital circuit in LTspice before.
I’ve attached the FlipFlop_SR_Clock circuit in Temp.
Thank you!
|
On Tue, May 27, 2025 at 10:27 AM, bwolfe58 wrote:
The first .MODEL statement is a single line of text but it is displayed as two lines in this response.
That depends on your browser's screen width.
?
The root cause of the original problem apparently was because the .model line had an errant "+" sign in the middle of it, which should not be there.? My guess is that the .model began life as two lines (with the required "+" continuation character), and someone thought they would be clever by combining both lines, but they forgot to remove the "+" sign - thus introducing improper syntax.
?
Andy
?
|
The first .MODEL statement is a single line of text but it is displayed as two lines in this response.
The second .MODEL statement is two lines with the + sign beginning the second line as shown.
|
On 27/05/2025 07:55, suded emmanuel via
groups.io wrote:
I just installed LTspice 24, I can use both old spice and
new, they both work!
I still need to auto generate the models used by old LTspice
(to build the symbols) to be able to use them in LTspice 24, is
there a way that I can use the models in the new LTspice 24 with
out regenerating please?
You are not very clear about what you have actually done.
Did you install LTspice 24 alongside your older existing version of
LTspice (presuming V17.x), or did you effectively perform an upgrade
over the top of your existing installation?
Or did you mean that old schematics created with your previous
version still work with the new version?
You are also not clear which version 24 you have just installed. I
presume you mean V24.1, since that is the latest one available on
ADI's website? (There are significant changes between 24.0 and
24.1.) Now we're at 24.1.8 (at the time of writing), most of the
initial issues arising have been addressed, but not all of them.
Whether you can use auto-generated symbols from your old version
depends whether they still exist. Did you back up the old libraries?
(BTW, you didn't auto-generate any models, it was the symbols you
auto-generated from the models. Or do I completely misunderstand
what you mean?) We can't know what you did unless you tell us. I
would advise anyway, that you get out of the habit of using
auto-generated symbols. There are several issues with them:
- They are hard-coded with your local machine's absolute path,
making sharing them problematic.
- They contain no information about the function
- They're ugly.
--
Regards,
Tony
|
There should be no need to regenerate anything
if you mean LTspice's native models. Version 24.1.x uses the
same models and symbols as version 17.x.x, and adds many new
ones. If you have actually found a problem, please explain more
clearly about it. You could look at 'Program Updates' in the FAQ
in the Help.
On 2025-05-27 06:55, suded emmanuel via
groups.io wrote:
Hi,
I just installed LTspice 24, I can use both old spice and
new, they both work!
I still need to auto generate the models used by old LTspice
(to build the symbols) to be able to use them in LTspice 24, is
there a way that I can use the models in the new LTspice 24 with
out regenerating please?
Regards,
Suded
--
Best wishes John Woodgate RAYLEIGH Essex OOO-Own Opinions Only
If something is true: * as far as we know - it's science *for
certain - it's mathematics *unquestionably - it's religion
|
Hi,
I just installed LTspice 24, I can use both old spice and new, they both work!
I still need to auto generate the models used by old LTspice (to build the symbols) to be able to use them in LTspice 24, is there a way that I can use the models in the new LTspice 24 with out regenerating please?
Regards,
Suded
|
The simulation runs without an error if you remove the "+" sign between RS= and CHT= in the model statement: RS=31.5 + CGS=2.25E-12.
The + sign was probably meant to be a continuation of the model statement to a second line.
?
Either of the following model statements simulate without an error:
?
.MODEL 2N5457 NJF(VTO=-1.8 BETA=0.00135 LAMBDA=0.001 RD=35 RS=31.5 CGS=2.25E-12 CGD=6E-12 KF=6.5E-17 AF=0.5 )
?
.MODEL 2N5457 NJF(VTO=-1.8 BETA=0.00135 LAMBDA=0.001 RD=35 RS=31.5?
+ CGS=2.25E-12 CGD=6E-12 KF=6.5E-17 AF=0.5 )
?
|
Re: Netlist fails to complete only on one computer
On 26/05/2025 06:55, david via
groups.io wrote:
Thanks for the quick reply!
?
I assume this is being run as a schematic, it is opend as
such and run with the "Run" command.?
?
For this file it appears to always be that .model line (line
86) where the truncation occurs.?
I just ran two other simulations that fail to run.
One is cutoff at line 85 (weirdly similar) on a "M8 0 N015 0 0
BS" line
The other cuts of on line 50 on a "X§U11 N018 N019 5 0 Isense
level2" line.
?
I agree that the hardware might be the issue. I have had
issues with this machine corrupting schematics in the past
wherein it was failing to save items on the schematic so other
computers opened a schematic with parts missing.?
These files are stored on google drive, so we are all getting
the same file - which is where my computer corrupting the files
becomes an issue.?
Running a schematic from a remote drive is usually a really bad
idea.
Unless you have set up LTspice to use other directories for files
written and read during an analysis, most i/o will be directed up to
the remote location and back down again. Furthermore, if this Google
drive is shared, which it sounds like it is, how do you ensure
different people are not trying to access the same files at the same
time?
Try copying the schematic to your computer and opening it from
there, and see if the issue changes.
--
Regards,
Tony
|
Re: Netlist fails to complete only on one computer
I think you should investigate the Windows
installation on that computer. Will it upgrade to Window 11? If
not, reinstall Windows 10 while you still can.
Hi Andy,?
?
Thanks for the quick reply!
?
I assume this is being run as a schematic, it is opend as
such and run with the "Run" command.?
?
For this file it appears to always be that .model line (line
86) where the truncation occurs.?
I just ran two other simulations that fail to run.
One is cutoff at line 85 (weirdly similar) on a "M8 0 N015 0 0
BS" line
The other cuts of on line 50 on a "X§U11 N018 N019 5 0 Isense
level2" line.
?
I agree that the hardware might be the issue. I have had
issues with this machine corrupting schematics in the past
wherein it was failing to save items on the schematic so other
computers opened a schematic with parts missing.?
These files are stored on google drive, so we are all getting
the same file - which is where my computer corrupting the files
becomes an issue.?
?
?
--
Best wishes John Woodgate RAYLEIGH Essex OOO-Own Opinions Only
If something is true: * as far as we know - it's science *for
certain - it's mathematics *unquestionably - it's religion
|
Re: Netlist fails to complete only on one computer
Hi Andy,?
?
Thanks for the quick reply!
?
I assume this is being run as a schematic, it is opend as such and run with the "Run" command.?
?
For this file it appears to always be that .model line (line 86) where the truncation occurs.?
I just ran two other simulations that fail to run.
One is cutoff at line 85 (weirdly similar) on a "M8 0 N015 0 0 BS" line
The other cuts of on line 50 on a "X§U11 N018 N019 5 0 Isense level2" line.
?
I agree that the hardware might be the issue. I have had issues with this machine corrupting schematics in the past wherein it was failing to save items on the schematic so other computers opened a schematic with parts missing.?
These files are stored on google drive, so we are all getting the same file - which is where my computer corrupting the files becomes an issue.?
?
?
|
Re: Netlist fails to complete only on one computer
I see it is different schematics (or netlist) that cause the same problem.
?
What can you tell us about the medium that holds the schematic or netlist that is to be run?
?
I wonder if it has errors being written to, or time-out errors.? Can you move the schematic to another medium and try again?
?
Andy
|
Re: Netlist fails to complete only on one computer
Is this being run as a Netlist, or a schematic?
?
Is it a random line where the truncation begins, or the same .model line each time?
?
The fact that it is the same hardware, but not the same LTspice version, suggests a hardware fault.? Maybe its drive is bad, or the copy of the schematic or netlist is corrupt on that one PC.
?
Andy
?
?
|
Netlist fails to complete only on one computer
Hi All,?
?
I am having an issue wherein the netlist for simulations fails to complete one on computer.?
The specific simulation seems not to matter, but it is only an issue with larger simulations.?
?
The netlist (View -> SPICE Netlist) gets cropped short - sometimes in the middle of a line. It appears as if a character limit or something gets hit.?
eg:
...
D1 N018 N017 BAT46WJ
X§M4 N028 N029 0 SQ2308CES
X§M6 N035 N036 0 SQ2308CES
X§Q7 LOAD_DETECT_B N034 N032 BSR16
X§Q9 N009 N012 0 PMBTA45
X§Q3 N019 N021 0 PMBTA45
.model D D
.lib C:\Users\djwnz\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\Users\djwnz\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 10000m
* SEP_FET
* POS_TERM
.model MYSW
the correct completion of this line would have been as follows and significantly more netlist should have followed it.
.model MYSW SW(Ron=1 Roff=10Meg Vt=.5 Vh=-.4)
The simulation then obviously fails to run as the netlist is not complete, the specific failure messages depend on what has been left out of the netlist file.?
?
This happens with a number of different schematics, but only ever on this one PC. The simulation itself runs fine on every other simulation that it has been tested on.?
?
The machine in question is running Windows 10 pro, and the PC has been restarted multiple times to try and get this to work.
The machine is running LTSpice 24.1.8, and this has been reinstalled a couple of times, and older versions of LTSpice have also been installed to test.
This issue has persisted through all of this.?
?
Does anyone have any idea what may be the casue of this issue, or what setting of my install or computer may be to blame?
?
Thanks!
|
Re: Question regarding transformer core library uploaded in files
By 'he', I suppose you mean Alexander
Bordodunov. I expect he applied Jiles-Atherton or another model
to many examples of B-H curves and tweaked the model for best
overall results.? It's actually a bit optimistic to expect one
model to work well for ferrites, silicon-iron and
high-permeability nickel-iron alloys.
On 2025-05-24 22:05, Vendy via
groups.io wrote:
C is the Magnetization
reversibility , I guess it should not affect the inductance
but I think A will affect when I tried altering the A value
higher and lower the inductance varies towards the saturation.
So hope its fine
But just wanna how did he get these values , I get these
values auto generated by the jiles atherton model from the B-H
curve points
Did he use some other model or the range is much higher/lower
than what I gave or is it something else , just curious?
--
Best wishes John Woodgate RAYLEIGH Essex OOO-Own Opinions Only
If something is true: * as far as we know - it's science *for
certain - it's mathematics *unquestionably - it's religion
|
Re: Question regarding transformer core library uploaded in files
C is the Magnetization reversibility , I guess it should not affect the inductance but I think A will affect when I tried altering the A value higher and lower the inductance varies towards the saturation. So hope its fine
But just wanna how did he get these values , I get these values auto generated by the jiles atherton model from the B-H curve points
Did he use some other model or the range is much higher/lower than what I gave or is it something else , just curious?
|
John Woodgate
Bell, Dave
Tony Casey