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Just a little FYI - The filename that Hawker used actually was "TL074.301". The "(43)" is an error code from LTspice.? It was rather bad of them (ADI) to append the error message onto the end of the

I am using LTspice Version 24.1.8 I copied and pasted the TL074 model netlist into a schematic and used the opamp2 symbol renamed TL074. Added ±15V supplies and hooked it up as an inverting gain of

Yes.? ?LTspice symbols are the same, and LTspice schematics are the same.? They didn't change.? You just have a case where the new installation does not know where your old custom symbols were.

Hi Tony, I will try to drop the habit of using Autogenerated symbols! this process is much easier now in Qspice you have it all within the file! I'm just trying to use the older models that I have in

Hi Tony, I installed V24.1, Both LTspices are working, I did not upgrade, Yes, auto generated the symbols from 3rd party models, I can still use them in old LTspice just like before How do I use the

It seems that there has to be a 'newline' character (ASCII 12) before the + in order for it to be accepted.

It appears that older versions of LTspice accepted that errant plus sign (+) in the middle of the .MODEL statement, which should not have been there.? But the latest version rejects it and tells you

I've uploaded a corrected version. FlipFlop_SR_Clock_eT.zip Also posted a photo

Ah! Unexpected Sent: Tuesday, May 27, 2025 12:41 PM To: [email protected] Subject: EXTERNAL: Re: [LTspice] Flip Flop and NAND gate Clk doesn't need to cross 50% of Vcc. Just needs to cross the ref

I hope we will soon get a long-term stable version, not too many versions ahead. -- This email has been checked for viruses by AVG antivirus software. www.avg.com

Works fine in 24.1.9 eT

Looks like the problem is not about what's inside the model. The error message is cryptic, but suggests something like a wrong file being called. Andy

Clk doesn't need to cross 50% of Vcc.? Just needs to cross the ref input voltage of the A-devices, which is 0.5 V unless changed. Andy

Until the first clock edge, the output is undefined, and just oscillates. [email protected]> wrote:

Ok so y'all caught an ancient 5457 model bug, that worked non the less before 24.1.x. Can you tell me what is wrong with the ancient TI TL074 model that has worked (though limited) forever until now?

NO difference, slightly surprisingly to me, because Clk never crosses 50% of Vcc Sent: Tuesday, May 27, 2025 10:51 AM To: [email protected] Subject: EXTERNAL: Re: [LTspice] Flip Flop and NAND gate Try

Try reducing the clock voltage to 1 volt. -- Best w

After all of the suggested fixes, the FF is toggling nicely, BUT Clk is running at 100kHz, but Q is outputting a 0-5V triangle wave at 78MHz Dave Sent: Tuesday, May 27, 2025 9:53 AM To:

also, I see you have a 5V clock signal, but are using 0/1 V levels for S and R signals. A-type elements (i.e., logic gates) default to 0/1 V logic levels. Read about A-type elements in help. Finally,

It looks to me like it's working. You have applied a steady High to the S input, and a Low to the R input.? So the Q output is driven High and Q/ is driven Low. Show us your truth table that says