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A negative resistance circuit with brief description has been uploaded to: /g/LTspice/album?id=301539

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Have fun

Jim

Andy,

I saw that.? Am going through advisories and FAQ? - currently the basic beginner's tutorial- and come up to speed with any and all of relevance.

Appreciate the leg up!

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William, k6whp
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"Cheer up, things could get worse. So I cheered up and things got worse."

RIAA is intended for audio applications. ?Why in the world would you even think of square wave input? OK, transient over-load behavior might be one reason, but I think that the OP is a long ways from that, yet.

I think I have the circuit you need. It is circa-1965 and uses 3-4 bipolar transistors, a zener diode, and a handful of resistors. All components are "garden variety" with nothing special. It works to a few MHz. It IS a 2-terminal device and can be used much like a tunnel diode. Voltages are a lot higher than a tunnel diode: peak voltage is around 2V, valley voltage is around 5V and peak current is a few 10s of mA; all of these values are settable as part of the circuit design. ?I have it ONLY as a PDF but it is simple enough to create in LTspice. I will put it, appropriately named, in the group image/picture directory and post a message with a link. This should be done within a few hours of this message time.

Andy,

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Thank you. I was to have uploaded the .asc file into temp per the group protocol but your answer will suffice. Appreciate the advisory and support.

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William, k6whp
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"Cheer up, things could get worse. So I cheered up and things got worse."

I uploaded your schematic file.? It is "RF_Filter_Chebyshev.asc" and it is currently in the Temp folder, in the group's Files section.

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Andy

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Andy,

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I did so instinctively and THEN read the group webpage. My apologies for the oversight.

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William, k6whp
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"Cheer up, things could get worse. So I cheered up and things got worse."

On Sat, Mar 29, 2025 at 08:48 PM, k6whp wrote:

I note that the display shows this model to initially be -6dB and wonder why.

It's a pretty simple reason, which looks obvious after you realize it.

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Your signal source has a 1 (volt) amplitude and 50 ohm source impedance.? It is a Thevenin source, so you've got 1 volt behind the 50 ohm source resistance.? When that is terminated (into a 50 ohm load), it is a voltage divider that cuts the voltage in half, so that the terminal voltage across V1 is 0.5 volt, resulting in a nominal 6 dB loss.

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When using AC sources like this, set their amplitude to 2 (volts), so that they make 1 (volt) when terminated.

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Andy

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On Sat, Mar 29, 2025 at 08:48 PM, k6whp wrote:

Am designing a low pass filter for the 20m amateur band, code below. (My apologies if this violates group protocol. Advise and I will adhere in the future.)?

Even better:? Why not read the group's guidelines on the main group webpage.

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You attempted to paste your schematic file into the message.? Never paste or attach any files into a group message.

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Andy

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Am designing a low pass filter for the 20m amateur band, code below. (My apologies if this violates group protocol. Advise and I will adhere in the future.)?

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I note that the display shows this model to initially be -6dB and wonder why. Again, truly a beginner. Links to appropriate material gratefully received.

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Thank you in advance.

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William, k6whp
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"Cheer up, things could get worse. So I cheered up and things got worse."

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Simply use six instances of your circuit on single page and modify connection\termination for each individual circuits.
Yes, it`s not elegant, but works as simple as hammer.

Not sure if some kind of "stepping" will work faster.

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On Sat, Mar 29, 2025 at 06:27 PM, <davitkharshiladze26@...> wrote:

I have made contact with PyLTspice developer, and he pointed out that It could not be sped up further.

I consider that an odd thing to say.

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On the one hand, it suggests that his program adds pre-programmed delays which can't be reduced further, without risk of failure.

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On the other hand, it suggests that he knows your circuit, and he's telling you it can't simulate faster.? How would be know that?? I think you were saying that the simulation itself (with just LTspice) is about 1 second (each time) and that 1 second is too slow.

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Andy

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On Sat, Mar 29, 2025 at 06:13 PM, <pilou@...> wrote:

It's OK now, I just uploaded it.

Yes Andy. Exactly.?

On Sat, Mar 29, 2025 at 06:19 PM, <davitkharshiladze26@...> wrote:

1 second is too much for my purposes, and runtime is 1 second whether I use LTspice or PyLTspice? to run the simulaiton

Is 1 second what LTspice reports in its .log file?? Or is that from looking at a clock on the wall, from start to finish?

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If it really takes 1 second to run a simulation, then perhaps that is what it needs, period.? You implied that your actual circuit is "large", so maybe it really needs that much time to converge on the operating point, and that's where most of the time goes.? It is possible that you can reduce the convergence time.

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It might also help to know what version of LTspice you are using.? It has gone through some rather significant changes in the last couple of years, and I would not rule out the possibility that run time got faster for some things but slower for others.

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Andy

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I have made contact with PyLTspice developer, and he pointed out that It could not be sped up further.

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Thank you for your attention

On Sat, Mar 29, 2025 at 05:35 PM, <davitkharshiladze26@...> wrote:

LTSpice generates .raw output files, noramlly.

Correct.

I am using PyLTSpice tp prepeare netlist before simulation. I am manually writing the netlist.

Hmm.? I see some confusion there.? Do you manually write the netlist, or does PyLTSpice write or alter the netlist?? Obviously, if PyLTSpice needs to add .NET commands, it must be writing a netlist file (perhaps after reading one without the .NET commands), so that could be one place where some delay gets added.

After simulation, I am gathering .raw files and reading info from them.

Do you mean that you manually gather and read the .raw files?? Or does PyLTSpice have a hand in doing that?

I also use PyLTSpice to directly run the simulation after the netlists are prepeared:

Got that.

LTC.run runs the simulator and LTC.wait_completion() waits for .raw generation to finish. ...

Hmm.? That sets off alarm bells in my head.? How does PyLTSpice actually wait for LTspice to finish generating the .raw file?? Does it periodically probe the .raw file, looking for some sort of signature indicating that it is finished?? Does it wait until no further writing happens to the .raw file for the last, I don't know, let's say 15 seconds?? Does it examine the .log file waiting for a completion signature, and then post-process the .raw file?? Does it wait for Windows to signal that the process it was asked to run (running LTspice) has finished?

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Any of these things MIGHT introduce delays, anywhere from milliseconds to dozens of seconds, depending on what it does and how.

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The runtime of these 2 functions are approximately 1 second, which is way too much for my purposes.

What 2 functions are you talking about?

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How much time is acceptable?

I feel like normal LTSpice simulation takes about the same time, though, as I mentioned, it is harder to measure

1 second is too much for my purposes, and runtime is 1 second whether I use LTspice or PyLTspice? to run the simulaiton

On Fri, Mar 21, 2025 at 01:48 PM, <pilou@...> wrote:

Sorry I'll uptload it again later.

It's OK now, I just uploaded it.

Sorry, I see that the author of PyLTSpice does not know how to spell "LTspice".

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LTspice has no capital "s".? It is spelled "LTspice".

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PyLTSpice has a capital "S".

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Humph.

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Andy

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