On Sat, Mar 29, 2025 at 06:27 PM, <davitkharshiladze26@...> wrote:

I have made contact with PyLTspice developer, and he pointed out that It could not be sped up further.

I consider that an odd thing to say.

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On the one hand, it suggests that his program adds pre-programmed delays which can't be reduced further, without risk of failure.

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On the other hand, it suggests that he knows your circuit, and he's telling you it can't simulate faster.? How would be know that?? I think you were saying that the simulation itself (with just LTspice) is about 1 second (each time) and that 1 second is too slow.

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Andy

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On Sat, Mar 29, 2025 at 06:13 PM, <pilou@...> wrote:

It's OK now, I just uploaded it.

Yes Andy. Exactly.?

On Sat, Mar 29, 2025 at 06:19 PM, <davitkharshiladze26@...> wrote:

1 second is too much for my purposes, and runtime is 1 second whether I use LTspice or PyLTspice? to run the simulaiton

Is 1 second what LTspice reports in its .log file?? Or is that from looking at a clock on the wall, from start to finish?

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If it really takes 1 second to run a simulation, then perhaps that is what it needs, period.? You implied that your actual circuit is "large", so maybe it really needs that much time to converge on the operating point, and that's where most of the time goes.? It is possible that you can reduce the convergence time.

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It might also help to know what version of LTspice you are using.? It has gone through some rather significant changes in the last couple of years, and I would not rule out the possibility that run time got faster for some things but slower for others.

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Andy

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I have made contact with PyLTspice developer, and he pointed out that It could not be sped up further.

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Thank you for your attention

On Sat, Mar 29, 2025 at 05:35 PM, <davitkharshiladze26@...> wrote:

LTSpice generates .raw output files, noramlly.

Correct.

I am using PyLTSpice tp prepeare netlist before simulation. I am manually writing the netlist.

Hmm.? I see some confusion there.? Do you manually write the netlist, or does PyLTSpice write or alter the netlist?? Obviously, if PyLTSpice needs to add .NET commands, it must be writing a netlist file (perhaps after reading one without the .NET commands), so that could be one place where some delay gets added.

After simulation, I am gathering .raw files and reading info from them.

Do you mean that you manually gather and read the .raw files?? Or does PyLTSpice have a hand in doing that?

I also use PyLTSpice to directly run the simulation after the netlists are prepeared:

Got that.

LTC.run runs the simulator and LTC.wait_completion() waits for .raw generation to finish. ...

Hmm.? That sets off alarm bells in my head.? How does PyLTSpice actually wait for LTspice to finish generating the .raw file?? Does it periodically probe the .raw file, looking for some sort of signature indicating that it is finished?? Does it wait until no further writing happens to the .raw file for the last, I don't know, let's say 15 seconds?? Does it examine the .log file waiting for a completion signature, and then post-process the .raw file?? Does it wait for Windows to signal that the process it was asked to run (running LTspice) has finished?

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Any of these things MIGHT introduce delays, anywhere from milliseconds to dozens of seconds, depending on what it does and how.

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The runtime of these 2 functions are approximately 1 second, which is way too much for my purposes.

What 2 functions are you talking about?

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How much time is acceptable?

I feel like normal LTSpice simulation takes about the same time, though, as I mentioned, it is harder to measure

1 second is too much for my purposes, and runtime is 1 second whether I use LTspice or PyLTspice? to run the simulaiton

On Fri, Mar 21, 2025 at 01:48 PM, <pilou@...> wrote:

Sorry I'll uptload it again later.

It's OK now, I just uploaded it.

Sorry, I see that the author of PyLTSpice does not know how to spell "LTspice".

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LTspice has no capital "s".? It is spelled "LTspice".

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PyLTSpice has a capital "S".

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Humph.

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Andy

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Help? me understand the problem.

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<davitkharshiladze26@...> wrote:

... However, simulation takes too much time. It takes 1 second for the simulation to complete. ...

On Sat, Mar 29, 2025 at 05:41 PM, alan victor wrote:

Use the educational examples, oscillators, Colpits and remove the resonating inductor leaving the active device and passive feedback?

elements in place. ...

I might be wrong, but I think alan is referring to one of the example schematics that installs on your computer's disk when you install LTspice.

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...\examples\Educational\Colpitts.asc

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Andy

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On Fri, Mar 28, 2025 at 11:53 AM, <sebastian.herrera@...> wrote:

Dear all, I am trying to simulate a circuit with negative conductance using transistors and passive components. Does anyone have a circuit for this?

Use the educational examples, oscillators, Colpits and remove the resonating inductor leaving the active device and passive feedback?

elements in place. Do a scattering parameter operation and note the modulus of S11 is > unity over the range of potential frequency

of operation. This yields negative conductance. Note there is a nice peak in negative G value in the 1-10 MHz range and extends out to ~ 40 MHz.?

LTSpice generates .raw output files, noramlly.

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I am using PyLTSpice tp prepeare netlist before simulation. I am manually writing the netlist.

After simulation, I am gathering .raw files and reading info from them.

I also use PyLTSpice to directly run the simulation after the netlists are prepeared:

LTC.run runs the simulator and LTC.wait_completion() waits for .raw generation to finish. Afterwards i can read these files for my desired outputs.

The runtime of these 2 functions are approximately 1 second, which is way too much for my purposes.

I feel like normal LTSpice simulation takes about the same time, though, as I mentioned, it is harder to measure

So -- what files does PyLTspice need to write and read?

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I still think (from your description) that this is the bottleneck.

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Andy

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No, I am not using .MEAS commands.

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I tried using some mechanisms that reduced filesize for .raw files, but results remained the same.

As far as I know, file reading and writing are part of the reported simulation time.

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You might affect that by controlling where it accesses those files, and how big they can be.

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Andy

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Wait - are you using .measure commands?? Is that where you see things slowing down?

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.MEAS commands are indeed processed after the simulation is over.

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Andy

Unfortunately, I can not use .STEP command.?

My main problem is finding multi-port s-parameters of a given circuit. LTSpice only supports 2-port s-parameters. To measure 4-port s-parameters I need to run simulation several times (6 times to be exact), where I change the port locations on each iteration. This requires me to slightly modify the netlist, meaning that I am running practically new simulation each time.

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Even when I run simulaiton using LTSpice it still takes approximately 1 second, thought, it is harder for me to measure, therefore, I feel the problem is within the simulator itself. I feel like the simulator needs time for initializing, file writting and so on. I have not found a way to disable any additional protocols.

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Thank you for your responses?

Can you re-do your sims using .STEP ?? Thus avoiding PyLTspice?

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Andy