Re: Problems using Pspice fet model for infineon BSR202N.
Bordodynov wrote, "but the temperature of the transistor chips is zero, which is not correct."
That happens because of the .TRAN ... STARTUP option, which starts the heatsink temperature at 0 instead of 50.? It takes a while for the junction temperature to catch up, because of the thermal lag of the transistor package internals.
That can be avoided by removing STARTUP.? Who needs it anyway?
I think it could also be avoided by putting the HEATSINK voltage source inside a subcircuit (because I believe STARTUP only affects sources at the top-level).? It can also be avoided by adding this statement:
.IC V(n001)=50 V(n003)=50
but then you really should name those two nodes!? (N001 = Tj of U2, N003 = Tj of U1.)
Regards, Andy
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Re: Problem with inserting components and drawing wires
Hello,
I searched a little bit with Google. Maybe this problem has to do with a mouse setting.
You could also try with another mouse.
Helmut
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Re: Problems using Pspice fet model for infineon BSR202N.
Hi richard. I made a solution to the problem of calculation, but the temperature of the transistor chips is zero, which is not correct. I do not like these models. To all, due to the complexity may be errors. See _sbb2_AB.zip in TEMP folder. ? Bordodynov.
16.11.2018, 09:35, "richard@... [LTspice]" :
?
I think you are right. I made a mistake. Sorry. sbb2.zip in the files area should demonstrate the problem. I will have a look at the help file you have refereed to. I have looked at similar files - and followed their suggestions with cshunt, gshunt, gmin etc without much luck. I agree it is probably a combination of the model and my circuit that is stressing LTspice. I can change out the BSR202N parts for "LTspice native parts" - and the circuit works. Also - Tony's circuit works with the model - so it does appear to be a combination. I'll let you now if I find a solution.
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Re: Problems using Pspice fet model for infineon BSR202N.
I think you are right. I made a mistake. Sorry. sbb2.zip in the files area should demonstrate the problem. I will have a look at the help file you have refereed to. I have looked at similar files - and followed their suggestions with cshunt, gshunt, gmin etc without much luck. I agree it is probably a combination of the model and my circuit that is stressing LTspice. I can change out the BSR202N parts for "LTspice native parts" - and the circuit works. Also - Tony's circuit works with the model - so it does appear to be a combination. I'll let you now if I find a solution.
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Re: introduction of a new vacuum tube spice model approach
Hi Andy
Thanks for your detailed response. Tomorrow, I will find time to optimize that. I see now the problem of an overloaded page...? 
regards, Adrian
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Re: Problems using Pspice fet model for infineon BSR202N.
Richard wrote:
? ? "I've uploaded BB2.zip with the circuit, asy and model files."
I think you made a mistake, because there is no BSR202N in that schematic.? Also no "timestep too small" error.? Must be the wrong schematic.
? ? "The main symptom is "Time step too small""
I urge you to download and read the "FAQ" file.? (Hint: It's in the "FAQ" folder in the Files section of the group.)? It has a section about "timestep too small" errors, which unfortunately happen from time to time in all SPICE programs.? There's a chance you can fix the simulation problem yourself.
"Timestep too small" often is not caused by one faulty model.? It's often a combination of things.
Another thing to consider, is using one of the other BSR202N models in Infineon's library file.
BSR202N BSR202N_L1 BSR202N_L0??
The L1 and/or L0 models might not end up with "timestep too small".? Also, they do not use the 5-pin symbol, so they do not include dynamic die temperature rise, which may or may not be an issue for you.? You could do the simulation at a higher SPICE temperature (or just set that MOSFET to the higher temperature), which is fine except that it keeps the temperature constant over time.
Regards, Andy
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Re: Behavioral source timestep limits ?
There are contradiction in real world ,too. If I just only study the textbook which contain lots math equations to describe the phenomemon of physics/electrics, etc. I tend to be confused, but if I just do the works ,practices of physical effort, I couldn't understand more deep theoretical mechanism behind, and unfortunately I, for an only one instance existing, I couldn't be two or more instances existing instantaneously to learn theory in the meanwhile do the practical things, and then connect them, so the fundamental materials is important, which is somewhat similar to , sometimes, we need to do FFT to transfer the time domain things to frequency domain, then revert the frequency domain things to time domain, make things simpler/clear to see, though the process is more complicated.
By the way, I really had suffered severe math equations confusion very badly, before . But, I still believe the learning curve of based on the basis/fundamental things ,finally would be likely the exp effect. Though, I don't think it's very impressive (I don't feel that / think so) , about the time step, but if you doubt or misunderstand.
Best regards. ---In LTspice@..., <ericsson.sunshine@...> wrote : Hello, Andy:
The mentioned ideas was not from me, and not related to what I said about 'confidential'. Just a brief, sudden thoughts, but I certainly remembered that someone who had written some thing about that (I surveyed that years ago) , though not very detailed about implementation. I guess its phase is not from detection, I would presume it's from pre-calculation, since many parameters could be obtained, Irms, Vrms, jwC, jwL, etc. Then generate whatever signal to the input of the compensation. The last thing is about the math & equations of math in the nature/circuits.
I know some of the rule of the nature, and some culture of some countries, but the world is huge, I don't understand everything, including rules everywhere and nowhere. But if possible, I would like keep going further, not for any matters, maybe for fun, I think.
Thank you very much. ---In LTspice@..., <ai.egrps@...> wrote : I still don't know what the Bv is for.
Since it represents an unreal component, are you thinking about using it to experiment with an altered circuit, before designing that "alteration" using real components?? Or do you want to add an extra signal into your circuit?? Otherwise, I can't imagine why a Bv would be a useful thing, here.
Regardless of the reason, you need to be more careful to consider the effect of adding the Bv to the existing circuit.? In both examples, it has a profound effect even though it is only a unity-gain buffer.? Remember that Bv unity-gain buffers have infinite input impedance and zero output impedance and are uni-directional, so breaking a connection and inserting a Bv source in its place, is a significant change.
I don't know whether the following might be useful.? But a simple Bv unity-gain buffer could be replaced by a unity-gain E-element.? As far as I know, E-elements do not have the restrictions that a Bv source might have.? Therefore, if you were concerned about those Bv-source restrictions, you could replace it by an E-element.? While it is true that LTspice sometimes elevates an E-element back to a B-element, I think that it does not for a simple linear buffer.? So, you could use an E-element to check whether changes to your simulations were due to Bv-source's peculiar limitations, or something else.
Regards, Andy
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Re: Problems using Pspice fet model for infineon BSR202N.
I have found and used the BSR202N model and test circuit from Tony(?) The test circuit worked - but in my circuit - I ma getting similar results to that from my original version of the infineon model. The main symptom is "Time step too small", but the behaviour of the circuit prior to the error - doesn't seem to make much sense to me. I've uploaded BB2.zip with the circuit, asy and model files. I've tried adding cshunt, gshunt, gmin and a few capacitors - but all to no avial. Any advice appreciated.
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Re: Behavioral source timestep limits ?
Hello, Andy:
The mentioned ideas was not from me, and not related to what I said about 'confidential'. Just a brief, sudden thoughts, but I certainly remembered that someone who had written some thing about that (I surveyed that years ago) , though not very detailed about implementation. I guess its phase is not from detection, I would presume it's from pre-calculation, since many parameters could be obtained, Irms, Vrms, jwC, jwL, etc. Then generate whatever signal to the input of the compensation. The last thing is about the math & equations of math in the nature/circuits.
I know some of the rule of the nature, and some culture of some countries, but the world is huge, I don't understand everything, including rules everywhere and nowhere. But if possible, I would like keep going further, not for any matters, maybe for fun, I think.
Thank you very much. ---In LTspice@..., <ai.egrps@...> wrote : I still don't know what the Bv is for.
Since it represents an unreal component, are you thinking about using it to experiment with an altered circuit, before designing that "alteration" using real components?? Or do you want to add an extra signal into your circuit?? Otherwise, I can't imagine why a Bv would be a useful thing, here.
Regardless of the reason, you need to be more careful to consider the effect of adding the Bv to the existing circuit.? In both examples, it has a profound effect even though it is only a unity-gain buffer.? Remember that Bv unity-gain buffers have infinite input impedance and zero output impedance and are uni-directional, so breaking a connection and inserting a Bv source in its place, is a significant change.
I don't know whether the following might be useful.? But a simple Bv unity-gain buffer could be replaced by a unity-gain E-element.? As far as I know, E-elements do not have the restrictions that a Bv source might have.? Therefore, if you were concerned about those Bv-source restrictions, you could replace it by an E-element.? While it is true that LTspice sometimes elevates an E-element back to a B-element, I think that it does not for a simple linear buffer.? So, you could use an E-element to check whether changes to your simulations were due to Bv-source's peculiar limitations, or something else.
Regards, Andy
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Hello,
LTspice has a phase comparator named "phidet". It*s in the folder [Digital].
The deafult output curernt is 100uA. This current can be set to any other value with Iout=xxx.
See the example? PLL2.asc in the folder Examples from your LTspice installation.
You can download another example from our Yahoo group. It demonstrates that "phidet" is the calssic two FF phase detector.
PHIDET_PFD1.asc
Best regards, Helmut
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Would anyone be able to direct me towards some accurate phase comparator circuits that I could build within LTspice XVII??
Thanks?
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Re: Behavioral source timestep limits ?
I still don't know what the Bv is for.
Since it represents an unreal component, are you thinking about using it to experiment with an altered circuit, before designing that "alteration" using real components?? Or do you want to add an extra signal into your circuit?? Otherwise, I can't imagine why a Bv would be a useful thing, here.
Regardless of the reason, you need to be more careful to consider the effect of adding the Bv to the existing circuit.? In both examples, it has a profound effect even though it is only a unity-gain buffer.? Remember that Bv unity-gain buffers have infinite input impedance and zero output impedance and are uni-directional, so breaking a connection and inserting a Bv source in its place, is a significant change.
I don't know whether the following might be useful.? But a simple Bv unity-gain buffer could be replaced by a unity-gain E-element.? As far as I know, E-elements do not have the restrictions that a Bv source might have.? Therefore, if you were concerned about those Bv-source restrictions, you could replace it by an E-element.? While it is true that LTspice sometimes elevates an E-element back to a B-element, I think that it does not for a simple linear buffer.? So, you could use an E-element to check whether changes to your simulations were due to Bv-source's peculiar limitations, or something else.
Regards, Andy
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Marcel wrote:
? ? "Still, they are all schematics created by this particular user. Maybe? ? ? ?he has a special lib, or uses specific LTspice features. It would help ? ? ?to see the smallest complete project that crashes."
Yup.? I think I acknowledged that already.
But it's even less likely to be the cause, because it only crashes when probing waveforms, not when drawing schematics or simulating them.? Once his signals are waveforms in a .raw file, it pretty doesn't matter how they got there.? (Yes there remains some chance that it could be something on his schematic, since he probably probes waveforms by clicking on schematic features.)
Regards, Andy
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Re: Problems using Pspice fet model for infineon BSR202N.
Hello Helmut,
I agree in principle for
transient simulations, but for DC sweeps it does make sense because the
case to junction temperature difference would otherwise be zero, as you say.
Regards, Tony
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Re: Problems using Pspice fet model for infineon BSR202N.
Hello Tony,
You
shouldn't normally connect a V-source to the output TJ, because this
pin is internally driven and shows the junction temperature. The output
will be very different when you remove V4, because the Mofet is going
hot in this test to many kilo-degree C when DC is applied.
On
the other hand it makes sense to put this V4, if you want a plot like
you did. This V4 will cancel thermal self heating effects.
Best regards, Helmut
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Re: Problems using Pspice fet model for infineon BSR202N.
richard@... wrote:
"Are there any "tricks of the trade" translating Pspice models for use in
LTspice? Not sure how to upload or share the models or ASC files. Happy
to do so with guidance."
This particular Infineon model (BSR202N) runs without any "translation" for LTspice. The Infineon models, in general, are extremely complex and often cause problems in LTspice, particularly in larger circuits. Most of them incorporate elaborate temperature modelling, so require inputs corresponding to the physical temperature of the junction, and also the case in this example. This library, as you surmised, therefore requires a 5 terminal symbol.
I have uploaded an example that shows how to use the extra pins on the 5 terminal symbol (also uploaded), and the simulation plots the drain characteristics when the case temperature is swept over the range 0 to 50¡ãC.
Files > Temp > BSR202N_Test.zip
The 5 terminal MOSFET symbol can be found somewhere in the files area (probably uploaded by Helmut some years ago), but I already had a copy of it, so I used that.
Regards, Tony
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Re: Problems using Pspice fet model for infineon BSR202N.
To upload, go to the web site, click on Files,
scroll to Temp and click on Upload. Upload a ZIP archive (not
any other sort) containing everything required to run the
simulation, but not .raw or .log files.
John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates
Rayleigh, Essex UK
toggle quoted message
Show quoted text
?
I am trying to use the Infineon supplied Pspice model for
this part (BSR202N). I've created (found) a 5 terminal
symbol to suit the model, but it makes no sense in an
LTspice simulation. If I replace the parts with native
LTspice NMOS parts, the simulation runs fine.
Are there any "tricks of the trade" translating Pspice
models for use in LTspice? Not sure how to upload or share
the models or ASC files. Happy to do so with guidance.
Thanks.
|
Problems using Pspice fet model for infineon BSR202N.
I am trying to use the Infineon supplied Pspice model for this part (BSR202N). I've created (found) a 5 terminal symbol to suit the model, but it makes no sense in an LTspice simulation. If I replace the parts with native LTspice NMOS parts, the simulation runs fine.
Are there any "tricks of the trade" translating Pspice models for use in LTspice? Not sure how to upload or share the models or ASC files. Happy to do so with guidance.
Thanks.
|
Re: Behavioral source timestep limits ?
For example, (not adapted by me), the typically active PF controller makes the PF upto very high 99%, but after EMI filter circuit added, maybe some phase difference may be caused, those phase difference causes cos(theta) decreases some, so if maybe improve it, but doing some compensation, such kinds of things. Especially when using in heavy loading. (Heavy EMI filter.)
Thank you very much. ---In LTspice@..., <ericsson.sunshine@...> wrote : Hello, Andy: Let me ask this:? What are you trying to do?? Why add the Bv sources?
Just some quick transfer trying for compensation to a newer shape as the secondary reference, concurrently with the first priority feedback still connected. The description expressed in the fashion of could apply to any topology.
Thank you for the suggestions.
Best regards.
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>? That's true.? But he says that it happens with many different ones?> ("all schematics")
Still, they are all schematics created by this particular user. Maybe? he has a special lib, or uses specific LTspice features. It would help to see the smallest complete project that crashes.
-marcel
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Tony Casey
John Woodgate