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开云体育

开云体育

Howdy

I am tying myself in knots trying to examine the buildup of phase in a relatively simple regulator circuit. ?I have uploaded Phase Analysis.zip to the files section. File darlington.asc contains two schematics, the second of which has been set up to examine phase and gain margin by breaking the feedback loop and inject AC small signal of 1. Run the simulation and plot -V(Vout_DD_stab)/V(Y) provides loop gain and phase. ?I read phase margin as the absolute difference between the reading for phase at the UGF and 0 or 180/-180 whichever is closer. ?In this case, I read -91 degrees for phase at UGF of 1.35Mhz and hence understand my phase margin is 89 degrees. (I understand that the -180 degree phase shift from the op amp inversion is omitted, presumably for simplicity.)

[Incidentally, a few days ago LTspice produced the plot in Phase and Gain Margin - old.jpg. Note the differences in gain below about 10kHz. That plot was produced in an earlier schematic. I later encountered problems with the schematic no longer recognising .inc statements and hence refusing to work. I therefore produced a new schematic from scratch but updated LTspice at the same time. I've examined every inch of the schematic and there are no differences that I can see from old to new (all components and values are the same) and yet, while the UGF and phase margin results are the same, the gain plot below 10kHz is significantly different and seemingly 'less correct.' At this stage I can only (very gingerly) conclude that this resulted from the update to LTspice. ?Eek...]

I now want to understand the contributors to the additional 91 degrees of phase shift and I am unsure of how best to probe the schematic when the loop is broken in this fashion. I have plotted several other traces.

A. ?-V(vout_dd_stab)/V(OA_Out2) is intended to look at the phase shift from feedback network through to the output of the op amp. (Perhaps I have to change the numerator and denominator to see a plot of -180 degrees.) In a perfect world I would expect to see a flat line at 180 degrees. ?

B. ?-V(vout_dd_stab)/V(Shift_Out2) is intended to add in the level shift network. As I would expect, judging from the lack of difference between this and the trace discussed above, the level shift is not contributing to phase shift.?

C. ?-V(vout_dd_stab)/V(Driver_Out2) is intended to add in the driver transistor EF. Given the very limited difference between this trace and those above I conclude there is little contribution to phase shift from the driver transistor.?

D. ?Presumably one would ordinarily conclude the balance of the (modelled) phase shift it coming from the pass transistor.?

Am I 'probing' the schematic in correct fashion? Is there an easier way? I don't seem to be able to use a differential probe to identify phase shift between two points. For example, it would seem 'natural'?(on a Mac)?to be able to place the probe on Shift_Out2, left-click and hold while dragging it to OA_Out2 before releasing in order to examine any phase shift from the level shift network. ?Doing so, however, does not produce a flat phase line at 0 which one would conclude from examining the (lack of difference between) the first two traces discussed above (A and B). How can I directly plot the phase shift contribution of the pass transistor to test D above? ?Ordinarily I would not have thought it would contribute any significant phase shift.?

Thanks in advance for any assistance

Steve

to go out on a whim of some marketing guy that prompts me to upgrade to his last contraption.

Been there, done that!

And now comes LTC (or shell I say ANALOG) with a new, 'improved" version of heir otherwise

decent simulator."