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Date

Re: Singleton amplifier loop gain simulation(Stability margins)

 

John,


R1 is a bias resistor to ensure?Q2s collector current is sufficient.? It also provides a path to discharge Q7s base when the AC voltage swings down.? C1 reduces the bandwidth of Q7.


Rick


Re: Singleton amplifier loop gain simulation(Stability margins)

John Woodgate
 

In message <l82hrs+nqehh0@...>, dated Sun, 8 Dec 2013,
vegetat55@... writes:

the file i posted is at?Files > Temp


named Singleton amplifier loop gain simulation(Gain & phase margins).as
What are C1 and R1 for? If you disable this network by making R1 = 1
meg, it seems to work as predicted.
--
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Nondum ex silvis sumus
John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK


Re: Singleton amplifier loop gain simulation(Stability margins)

 

the file i posted is at?Files > Temp


named Singleton amplifier loop gain simulation(Gain & phase margins).asc


Re: Singleton amplifier loop gain simulation(Stability margins)

John Woodgate
 

In message <l82gt4+nphhn5@...>, dated Sun, 8 Dec 2013, vegetat55@... writes:

Hello. I am trying to simulate the loop gain of this kind of amplifier but i cant. i want to find gain margin and phase margin.can you help?


I uploaded LTspice file in temp folder here:
Please upload the schematic, not the net list. It's far easier to help with a schematic.
--
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Nondum ex silvis sumus
John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK


Singleton amplifier loop gain simulation(Stability margins)

 

Hello. I am trying to simulate the loop gain of this kind of amplifier but i cant. i want to find gain margin and phase margin.can you help?


I uploaded LTspice file in temp folder here: ?


Re: Specifiying multiple grounds in LTspice

 

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Le 08/12/2013 14:07, Andy a ¨¦crit?:
?


The only LTspice requirement, is that every circuit node must have a DC path to GND ...

Some people don't seem to like that, if they have a circuit with an isolation transformer that keeps a part of their circuit actually isolated from the GND that appears elsewhere in their circuit.?
I believe the reason is when a transformer is properly modelled with its stray capacitances, the results will be different in function of the way the floating part is made non-floating.
Particularly there will be a big difference with one leg of the output directly connected to ground compared to having both legs connected via 1Meg resistors.

This limitation of LTspice is not a problem for me, since it is part of my routine to evaluate transformers with all sorts of connections, unbalaned in particular.
I must admit this limitation may be a hindrance for users who are not comfortable with transformers intricacies.


Re: Spice model locations

 

Smart! I have never thought of doing that. I include additional files in some of my subcircuits/lib files, but I still have to .inc my subcircuit. I will try your trick!


Re: Specifiying multiple grounds in LTspice

 

Dhara?wrote:

?Therefore I would like to specify two different grounds. Is this actually possible in LT spice?


There's nothing stopping you from having any number of so-called "grounds" (in sloppy electrical circuit parlance), as long as you give all of them different names. ?GND1, GND2, ground3, myground, etc. ?They are just nets with net names.

The unique Ground symbol couldn't be used for them all, of course.

Do you need a "ground" symbol on your schematics for the different grounds? ?You could create your own unique symbols and use those. ?LTspice itself does have a second symbol, COM, which you can use however you wish. ?All it is, is a node, which isn't the same as GND (= node 0). ?It has no other significance.

The only LTspice requirement, is that every circuit node must have a DC path to GND. ?That's because LTspice needs to calculate the actual voltage on every net, relative to GND, and in order to do that, the DC circuit must have a conductive path that eventually leads to GND.

Some people don't seem to like that, if they have a circuit with an isolation transformer that keeps a part of their circuit actually isolated from the GND that appears elsewhere in their circuit. ?But it really doesn't matter. ?If the isolated portion is truly isolated, then it will function just as well if they connected it to GND anyway ... or to 7V, or to 7 million volts ... right? ?So, for circuit simulation purposes, it works fine to simulate it with the "floating" part connected to GND, either directly or through a big resistor. ?There just needs to be SOME path back to GND.

Regards,
Andy



Re: INA128 SpiceModel

 

Hello,

You have most probably defined too high numbers in the symbol's "Netlist Order".
These numbers should be 1,2,3,4,5,6,78 in the order of the .subckt line.


I have uploaded two examples INA128_test.zip and INA129_test.zip.

Just unzip it into any folder to RUN these examples.

http://groups.yahoo.com/neo/groups/LTspice/files/%20Lib


I highly recommend to always copy the symbol file and the model file into the folder of the schematic. Don't copy it into the installation folder of LTspice.


Best regards,

Helmut



*???????????????????????? |?? -
*???????????????????????? |?? |?? V+
*???????????????????????? |?? |?? |?? V-
*???????????????????????? |?? |?? |?? |?? Out
*???????????????????????? |?? |?? |?? |?? |?? REF
*???????????????????????? |?? |?? |?? |?? |?? |?? RG1
*???????????????????????? |?? |?? |?? |?? |?? |?? |?? RG2
*???????????????????????? |?? |?? |?? |?? |?? |?? |?? |
* PIN CONFIG FOR INA128?? 1?? 2?? 3?? 4?? 5?? 8?? 9? 10
**

.SUBCKT INA128???????? 1?? 2?? 3?? 4?? 5?? 8?? 9? 10


Netlsit order:

1 2 3 4 5 6 7 8




---In LTspice@..., <alihadidjafils88@...> wrote:

Hi,
i've tried to import the instrumentation amplifier INA128 spicemodel into LTspice but it did not word. The problem is in the spicemodel the pin are numbered sa below : 1 2 3 4 5 8 9 10. the 6th and the 7th pin are not available. when i run the simulation, this follow message appears to the display : "port pin count mismatch between the definition of sub circuit ina128 and instance ''xu1'' ". I do not know how to do, please help me. one more thing, i've created a new symbol because the Instrumentation Amplifier does not exist in LTspice.
i'm looking for your help asap.


Re: Specifiying multiple grounds in LTspice

 

you may right-click on the wire and chose "label", and there you have ground and com ... which is the one you seek.


Re: Spice model locations

 

I created the links, but instead of using a .inc file, put the equivalent path into the custom symbol for the path to the MyLib. ?Your help is much appreciated, thanks.


Re: Specifiying multiple grounds in LTspice

John Woodgate
 

In message <l81ap6+19csfea@...>, dated Sun, 8 Dec 2013, the_sky_falcon_1982@... writes:

It would be great if someone could shed some light on this problem.
GROUND 101

The problem is actually with the concept of 'ground', which is different in real life (and different there from what most people think it is) and what it is in Spice.

In real life, ground is simply a place assumed [*] to be at zero voltage, to which all other voltages are referred, and nothing to do with any planets or soil. Consider an aircraft, for example. Its 'ground' is probably the airframe.

While your transmitter and receiver are not electrically connected, their zero-voltage references could be connected together, without making any difference to their operation. This is good, because Spice will normally not work if a schematic has isolated circuits, not connected to anything else. Spice schematics must have a ground symbol (triangle) attached to the zero-voltage reference wire.

So for simulation purposes, you just add a fictitious connection between the 'grounds' of the transmitter and receiver. In a case where part of a circuit really has to have a high impedance relative to another part, you join its 'ground' to the other 'ground' via a high value resistor, but don't make it higher than necessary as this may cause convergence problems.

[*] Note 'assumed'. Other than superconductors, everything in real life has some impedance - resistance and inductance - so there can and will be a voltage between any two points on a 'ground' conductor that is carrying current. For correct operation, any such voltage must be so small as to be negligible. This can be done at low frequencies but when the dimensions of the ground are comparable with the free-space wavelength of the signal, such voltages will not be negligible.
--
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Nondum ex silvis sumus
John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK


Specifiying multiple grounds in LTspice

 

Hi all,

?

I would like to know how to specify different ground planes in ltspice. What I would like to do is to simulate a resonant wireless power transfer circuit. The transmitter side is a resonant circuit implemented using MOSFETS and comparators. The receiver is a tuned LC circuit. I aim to simulate the transmitter and the receiver side circuits in a single schematic.?(without modelling my transmitter circuit as a current source). The grounds of the transmitter and the receiver circuits are not the same. Therefore I would like to specify two different grounds. Is this actually possible in LT spice?

?

I would also like to simulate the induced voltage on my receiver coil (L) using a behavioural source. Again I have a problem with ground.

?

It would be great if someone could shed some light on this problem.

?

Thank you,

?

Dhara


INA128 SpiceModel

 

Hi,
i've tried to import the instrumentation amplifier INA128 spicemodel into LTspice but it did not word. The problem is in the spicemodel the pin are numbered sa below : 1 2 3 4 5 8 9 10. the 6th and the 7th pin are not available. when i run the simulation, this follow message appears to the display : "port pin count mismatch between the definition of sub circuit ina128 and instance ''xu1'' ". I do not know how to do, please help me. one more thing, i've created a new symbol because the Instrumentation Amplifier does not exist in LTspice.
i'm looking for your help asap.


Re: I added a CD4007 model

 

True, but that one's transistors' model is more off than this one, and there is no proper symbol that goes with it. I tried that model and I was not happy at all. For the vast majority of my projects a simple model is far better than the one with all the perks attached.
I've tried some models that at first seemed more elaborate than this one, and they mostly sucked at DC, and took forever to converge in transient. I can imagine several applications where various parasitics come to play, but the funniest part is that people who push the models to the limit often use only W and L and nothing else.

Replacing the model I supplied is incredibly easy, so whoever has a better model than this one, please share it.

I tried also this:

.model NMOS NMOS LEVEL=1 VTO=1.4
+ L=5e-6 W=124e-6 TOX=1080e-10
+ LAMBDA=0.01 KP=20e-6 PHI=0.6 GAMMA=1.5
**
.model PMOS PMOS LEVEL=1 VTO=-1.4
+ L=5e-6 W=480e-6 TOX=1080e-10
+ LAMBDA=0.02 KP=6e-6 PHI=0.6 GAMMA=1.5

and this:

.model NMOS NMOS Level=1 Gamma=0
+ Tox=1200n Phi=.6 Rs=0 Kp=111u Vto=2.0
+ Lambda=0.01 Rd=0 Cbd=2.0p Cbs=2.0p
+ Pb=.8 Cgso=0.1p Cgdo=0.1p Is=16.64p N=1
**
.model PMOS PMOS Level=1 Gamma=0
+ Tox=1200n Phi=.6 Rs=0 Kp=55u Vto=1.5
+ Lambda=0.04 Rd=0 Cbd=4.0p Cbs=4.0p
+ Pb=.8 Cgso=0.2p Cgdo=0.2p Is=16.64p N=1

and also this one that performed much better than the rest of them:
(attributed by kcin_melnick, see message #16897)
?
.MODEL NMOS NMOS (
+ LEVEL=1 VTO=1.44 KP=320u L=10u W=30u GAMMA=0 PHI=.6 LAMBDA=10m
+ RD=23.2 RS=90.1 IS=16.64p CBD=2.0p CBS=2.0p CGSO=0.1p CGDO=0.1p
+ PB=.8 TOX=1200n)
?
.MODEL PMOS PMOS (
+ LEVEL=1 VTO=-1.2 KP=110u L=10U W=60U GAMMA=0 PHI=.6 LAMBDA=40m
+ RD=21.2 RS=62.2 IS=16.64P CBD=4.0P CBS=4.0P CGSO=0.2P CGDO=0.2P
+ PB=.8 TOX=1200N)



The last one has also more realistic DC transfer. I could go with that one.


Re: PWMs and Darlingtons

Dan Fish
 

¿ªÔÆÌåÓý

Did you look at LTC6992-x in the special functions library?? LTC has an Excel-based design tool for all these timerblock products.
?
Dan
?

I'm new to ltspice, and am trying to draw and simulate a circuit.

This includes a PWM output and a darlington transistor; I searched the libraries and downloaded a new bjt library, but it doesn't contain a TIP120 I also need a pointer to a "signal generator" square wave with a variable duty cycle.

Any help?

Ed


Re: I added a CD4007 model

 

Hello

There is another example "" with the CD4007 in our Files section.


http://groups.yahoo.com/neo/groups/LTspice/files/%20Lib/


Best regards,

Helmut


Re: I added a CD4007 model

 

Hello,

The model DC characteristic may be ok, but? model with no capacitances is not reasonable.? You might be better off using LTspice logic devices.

Rick



On Saturday, December 7, 2013 6:46 PM, "davorslistdepot@..." wrote:
?
Hi all,
I was missing a CD4007 model, so there it is.
It is bare bones hierarchical model (so far) that I left that way so that it is easier to check what I did. If everything goes well, I'll make a subcircuit out of it.
The transistors models are based on the 4007 library used at csupomona.edu, like this:

.model NMOS NMOS LEVEL=2 VTo=1.4 Kp=.6m LAMBDA=0.005

.model PMOS PMOS LEVEL=2 VTo=-1.0 KP=.6m LAMBDA=0.01

No diodes or capacitances, and no resistors in this model. Just MOSFETs. Surprisingly this simple model produces a very nice Rds_on transfer plot, and triggers no alarms in error log.
So far I'm happy with it.

In CD4007L2_h.asc which is a hierarchy file i placed some comments about an easy way procedure of making a symbol out of a hierarchy, but please don't consider it a tutorial of any kind.



Re: I added a CD4007 model

 

Hello,

The model DC characteristic may be ok, but? model with no capacitances is not reasonable.? You might be better off using LTspice logic devices.

Rick



On Saturday, December 7, 2013 6:46 PM, "davorslistdepot@..." wrote:
?
Hi all,
I was missing a CD4007 model, so there it is.
It is bare bones hierarchical model (so far) that I left that way so that it is easier to check what I did. If everything goes well, I'll make a subcircuit out of it.
The transistors models are based on the 4007 library used at csupomona.edu, like this:

.model NMOS NMOS LEVEL=2 VTo=1.4 Kp=.6m LAMBDA=0.005

.model PMOS PMOS LEVEL=2 VTo=-1.0 KP=.6m LAMBDA=0.01

No diodes or capacitances, and no resistors in this model. Just MOSFETs. Surprisingly this simple model produces a very nice Rds_on transfer plot, and triggers no alarms in error log.
So far I'm happy with it.

In CD4007L2_h.asc which is a hierarchy file i placed some comments about an easy way procedure of making a symbol out of a hierarchy, but please don't consider it a tutorial of any kind.



Re: PWMs and Darlingtons

 

Ed,

SPICE doesn't have built in signal source with a variable duty cycle.? It is easy to build one with a comparator where one input is a triangular waveform and the other is a control signal that causes the duty cycle to vary.? I have done this with BV source as the comparator.? Search the group files and messages for PWM demo.

Rick



On Saturday, December 7, 2013 6:36 PM, texasham10 wrote:
?
I'm new to ltspice, and am trying to draw and simulate a circuit.

This includes a PWM output and a darlington transistor; I searched the libraries and downloaded a new bjt library, but it doesn't contain a TIP120 I also need a pointer to a "signal generator" square wave with a variable duty cycle.

Any help?

Ed