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Please leave schematic files as files, and upload them to the Temp folder.
Pasting them into an email makes for extra tedious work.

Your simulation severely over-stresses the op-amp. Its absolute maximum
power supply (Vdd-Vss) is 6.5V, with 5.5V being the recommended maximum.
Here you have applied 30V. That would surely fry the real op-amp.

The input amplitude also needs to be reduced, to keep the output from
saturating. Try setting it to 0.1V instead of 1.0V.

The simulation does seem to have difficulty if the amplitude is increased,
along with the 100ns rise and fall times (generating "timestep too small"
errors). Try backing them off to 1us rise and fall times and then the
amplitude can be increased. Perhaps the model doesn't like very fast input
slew rates.

Andy

Instance "m:u1:14": Length shorter than recommended for a level 1 MOSFET.
Instance "m:u1:12": Length shorter than recommended for a level 1 MOSFET.
Direct Newton iteration failed to find .op point. (Use ".option noopiter" to skip.)
Starting Gmin stepping
Increasing initial diagonal Gmin to 100
Increasing initial diagonal Gmin to 1000
Increasing initial diagonal Gmin to 10000
Increasing initial diagonal Gmin to 100000
Gmin = 100000
Gmin = 10737.4
Gmin = 1152.92
Gmin = 123.794
Gmin = 13.2923
Gmin = 1.42725
vernier = 0.5
vernier = 0.25
vernier = 0.125
vernier = 0.0625
Gmin = 1.32263
vernier = 0.03125
vernier = 0.015625
vernier = 0.0078125
vernier = 0.00390625
Gmin = 1.30727
vernier = 0.00195313
vernier = 0.00260417
Gmin = 1.30154
vernier = 0.00347222
vernier = 0.00462963
Gmin = 1.29076
vernier = 0.00617283
Gmin = 1.27346
vernier = 0.00823044
vernier = 0.0109739
Gmin = 1.24563
vernier = 0.0146319
vernier = 0.0195092
Gmin = 1.2028
vernier = 0.0260122
Gmin = 1.13645
vernier = 0.034683
vernier = 0.046244
Gmin = 1.03577
vernier = 0.0616586
vernier = 0.0822114
Gmin = 0.894523
vernier = 0.109615
Gmin = 0.705843
vernier = 0.146154
vernier = 0.194871
Gmin = 0.480262
vernier = 0.259828
vernier = 0.346438
Gmin = 0.262686
vernier = 0.461917
Gmin = 0.100406
vernier = 0.615889
vernier = 0.821185
Gmin = 0.0217694
vernier = 1
vernier = 0.5
vernier = 0.25
Gmin = 0.00509242
vernier = 0.125
vernier = 0.0625
vernier = 0.03125
vernier = 0.015625
vernier = 0.0078125
vernier = 0.00390625
vernier = 0.00195313
vernier = 0.000976563
vernier = 0.000488281
Gmin = 0
Gmin = 0
Gmin stepping failed

Starting source stepping with srcstepmethod=0
Source Step = 3.0303%
Source Step = 33.3333%
Source Step = 63.6364%
Source Step = 93.9394%
Source stepping succeeded in finding the operating point.

Heightened Def Con from 1.32884e-008 ++++++++++++++++++++++++++++++++++++++++++++++++++Fatal Error: Analysis: Time step too small; time = 1.32884e-008, timestep = 1.25e-019: trouble with node "u1:30"

test_mcp6xx.asc

Version 4
SHEET 1 880 708
WIRE -128 -16 -192 -16
WIRE -16 -16 -48 -16
WIRE 48 -16 -16 -16
WIRE 208 -16 128 -16
WIRE -192 16 -192 -16
WIRE 112 112 112 96
WIRE -16 128 -16 -16
WIRE 80 128 -16 128
WIRE 208 144 208 -16
WIRE 208 144 144 144
WIRE 272 144 208 144
WIRE -128 160 -192 160
WIRE 80 160 -48 160
WIRE -480 192 -480 176
WIRE -352 192 -352 176
WIRE -192 192 -192 160
WIRE 112 208 112 176
WIRE -480 288 -480 272
WIRE -352 288 -352 272
WIRE -192 288 -192 272
FLAG 112 96 VCC
FLAG 112 208 VSS
FLAG -192 288 0
FLAG -480 288 0
FLAG -352 288 0
FLAG -480 176 VCC
FLAG -352 176 VSS
FLAG -192 16 0
FLAG 272 144 out
IOPIN 272 144 Out
FLAG -192 160 in
SYMBOL voltage -192 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 .1u .1u 9.9u 20u)
SYMBOL voltage -480 176 R0
SYMATTR InstName V2
SYMATTR Value +15V
SYMBOL voltage -352 176 R0
SYMATTR InstName V3
SYMATTR Value -15V
SYMBOL res 32 0 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL res -144 0 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 2.5k
SYMBOL res -144 176 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL MCP63X 112 144 R0
SYMATTR InstName U1
TEXT -472 -128 Left 2 !.tran 40u
TEXT -472 -96 Left 2 !.options plotwinsize=0

Here is a bit of netlist code that uses the part. Almost everyone here
prefers a schematic (.asc), but plain netlists work too.

Vdd Vdd 0 2.5V
Vss Vss 0 -2.5V
Vsig sig 0 sine (0V 1V 1kHz) AC 1V
Rin sig inp 1k
Rfb out inn 5k
Rg inn 0 5k
X1 inp inn vdd vss out mcp63x
.tran 100ms
*.ac dec 10 1Hz 100MEGHz

And of course you need a Title line and an .END line, and your model.

Andy

any simple circuit with direct access, 2 resistor, the output to the input sine-wave signal

;
_DfFYpHOHVP4uZtI4zOKW21mBoXpU2Hk1ExJHaZw2yUQdn7KAp-o/%20Temp/MCP6xx.zip

vtlya2000 wrote:

please give me the simple working model?

The working model is the one you already provided! I used it in a
simulation, and it worked.

The model is a subcircuit. Think of it like an IC. If someone hands you
and IC, what are you going to do with it? You will probably hook it up to
some power supplies, add a few resistors, and a signal source of some sort.
An IC op-amp doesn't do anything all by itself until you add power, and an
external circuit!

A SPICE/LTspice/PSPICE/HSPICE/ISSPICE/XSPICE/etc. simulation of a device
model, doesn't do anything unless you provide it with the rest of the stuff
it needs to make a complete circuit.

So what was the circuit YOU used to test it?

Andy

please give me the simple working model?

vtlya2000 wrote:

problem is no work model parameter

?? What does this mean? What model parameter?

Andy

vtlya2000 wrote:

do not work

I tried the model in a simple circuit, and it worked for me, in both
transient and AC analysis.

Andy

yes, in no problem ))

problem is no work model parameter

By examining this model, there is a potential problem, but I think it
doesn't actually cause an error in LTspice:

.SUBCKT MCP63x 1 2 3 4 5

...

.ENDS MCP631

Notice how the name of the subcircuit (MCP63x) does not match the name
(MCP631) in the .ENDS statement. That tells me whoever constructed this
model was careless, which makes the model suspect. Those kinds of problems
are best resolved by contacting the company and telling them to fix their
model.

But as I say, I don't think the above mismatch actually causes a problem in
LTspice.

Andy

vtlya2000 wrote:

How to convert Microchip model to LtSpice?

This model already is a SPICE model. Why do you think it needs to be
converted?

do not work

That is a very unhelpful description. Please tell us WHAT did not work.
Please show us the simulation (schematic or netlist) that uses this model,
and what error messages you encountered.

Andy

How to convert Microchip model to LtSpice?

do not work

.SUBCKT MCP63x 1 2 3 4 5
* | | | | |
* | | | | Output
* | | | Negative Supply
* | | Positive Supply
* | Inverting Input
* Non-inverting Input
*

* Software License Agreement *
* *
* The software supplied herewith by Microchip Technology Incorporated (the *
* 'Company') is intended and supplied to you, the Company's customer, for use *
* soley and exclusively on Microchip products. *
* *
* The software is owned by the Company and/or its supplier, and is protected *
* under applicable copyright laws. All rights are reserved. Any use in *
* violation of the foregoing restrictions may subject the user to criminal *
* sanctions under applicable laws, as well as to civil liability for the *
* breach of the terms and conditions of this license. *
* *
* THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES, WHETHER *
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED *
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO *
* THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR *
* SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. *

*
* The following op-amps are covered by this model:
* MCP631, MCP632, MCP633, MCP635
*
* Revision History:
* REV A: 17-Jun-10, Created model
* REV B: 01-Nov-11, Fixed Vout swing issue
*
* Recommendations:
* Use PSPICE (or SPICE 2G6; other simulators may require translation)
* For a quick, effective design, use a combination of: data sheet
* specs, bench testing, and simulations with this macromodel
* For high impedance circuits, set GMIN=100F in the .OPTIONS statement
*
* Supported:
* Typical performance for temperature range (-40 to 125) degrees Celsius
* DC, AC, Transient, and Noise analyses.
* Most specs, including: offsets, DC PSRR, DC CMRR, input impedance,
* open loop gain, voltage ranges, supply current, ... , etc.
* Temperature effects for Ibias, Iquiescent, Iout short circuit
* current, Vsat on both rails, Slew Rate vs. Temp and P.S.
*
* Not Supported:
* Some Variation in specs vs. Power Supply Voltage
* Vos distribution, Ib distribution for Monte Carlo
* Distortion (detailed non-linear behavior)
* Some Temperature analysis
* Process variation
* Behavior outside normal operating region
*
* Input Stage
V10 3 10 1.1
R10 10 11 200K
R11 10 12 200K
G10 10 11 10 11 5M
G11 10 12 10 12 5M
C11 11 12 3P
C12 1 0 9P
E12 71 14 POLY(4) 20 0 21 0 26 0 27 0 3M 51 51 1 1
G12 1 0 62 0 1m
G13 1 2 63 0 1u
I12 1 0 -3p
M12 11 14 15 15 NMI
M14 12 2 15 15 NMI
G14 2 0 62 0 1m
C14 2 0 9P
I15 15 4 25M
V16 16 4 -300M
GD16 16 1 TABLE {V(16,1)} ((-100,-1p)(0,0)(1m,1u)(2m,1m)(3m,10))
V13 3 13 1.3
GD13 2 13 TABLE {V(2,13)} ((-100,-1p)(0,0)(1m,1u)(2m,1m)(3m,10))
R71 1 0 15E12
R72 2 0 15E12
R73 1 2 20E12
*
* Noise, PSRR, and CMRR
I20 21 20 423U
D20 20 0 DN1
D21 0 21 DN1
C20 20 22 3.6u
C21 21 23 3.6u
R22 22 0 1.5
R23 23 0 1.5
C22 22 24 2.2u
C23 23 25 2.2u
R24 24 0 5
R25 25 0 5
C24 24 241 .1u
C25 25 251 .1u
R241 241 0 10
R251 251 0 10
C241 241 0 .45u
C251 251 0 .45u
G26 0 26 POLY(2) 3 0 4 0 0.00 -40U -50U
R26 26 0 1
G27 0 27 POLY(2) 1 0 2 0 0 0.6M 0.6M
R27 27 0 1
L27 27 271 .23u
R271 271 0 .1
*
* Open Loop Gain, Slew Rate
G30 0 30 12 11 1
R30 30 0 1.00K
G31 0 31 3 4 -1
I31 0 31 DC 49.5
R31 31 0 1 TC=3.01M,-4U
GD31 30 0 TABLE {V(30,31)} ((-100,-1n)(0,0)(1m,0.1)(2m,10))
G32 32 0 3 4 9
I32 32 0 DC 42.5
R32 32 0 1 TC=2.2M,-3.59U
GD32 0 30 TABLE {V(30,32)} ((-2m,10)(-1m,0.1)(0,0)(100,-1n))
G33 0 33 30 0 1m
R33 33 0 1K
G34 0 34 33 0 1.4
R34 34 0 1K
C34 34 0 7U
G37 0 37 34 0 1m
R37 37 0 1K
C37 37 0 3P
G38 0 38 37 0 1m
R38 39 0 1K
L38 38 39 2.2U
E38 35 0 38 0 1
* Changed G35 and G36 to fix output offset - AR / 01-Nov-11
G35 33 0 TABLE {V(35,3)} ((-1,-1n)(0,0)(5.5,1n))(6.00,1))
G36 33 0 TABLE {V(35,4)} ((-6.00,-1)((-5.5,-1n)(0,0)(1,1n))
*
* Output Stage
R80 50 0 100MEG
G50 0 50 57 96 2
R58 57 96 0.50
R57 57 0 14.0
C58 5 0 2.00P
G57 0 57 POLY(3) 3 0 4 0 35 0 0 32M 31M 81M
GD55 55 57 TABLE {V(55,57)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
GD56 57 56 TABLE {V(57,56)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
E55 55 0 POLY(2) 3 0 51 0 -2.4M 1 -8.9M
E56 56 0 POLY(2) 4 0 52 0 1.24M 1 -8.5M
R51 51 0 1k
R52 52 0 1k
GD51 50 51 TABLE {V(50,51)} ((-10,-1n)(0,0)(1m,1m)(2m,1)(3m,100))
GD52 50 52 TABLE {V(50,52)} ((-3m,-100)(-2m,-1)(-1m,-1m)(0,0)(10,1n))
C51 50 51 2p
C52 50 52 2p
G53 3 0 POLY(1) 51 0 -25.0M 1M
G54 0 4 POLY(1) 52 0 -25.0M -1M
*
* Current Limit
G99 96 5 99 0 1
R98 0 98 1 TC=0.00,0.00
G97 0 98 TABLE { V(96,5) } ((-11.0,-80.0M)(-1.00M,-79.2M)(0,0)(1.00M,79.2M)(11.0,80.0M))
E97 99 0 VALUE { V(98)*((V(3)-V(4))*-31.2M + 1.07)}
D98 4 5 DESD
D99 5 3 DESD
*
* Temperature / Voltage Sensitive IQuiscent
R61 0 61 1 TC=2.54M,-5.92U
G61 3 4 61 0 1
G60 0 61 TABLE {V(3, 4)}
+ ((0,0)(1.00,10U)(1.2,0.1M)(1.45,1.4M)
+ (1.6,1.7M)(1.8,1.8M)(6.5,2.9M))
*
* Temperature Sensitive offset voltage
I73 0 70 DC 1uA
R74 0 70 1 TC=2.00
E75 1 71 70 0 -1
*
* Temp Sensistive IBias
I62 0 62 DC 1uA
R62 0 62 REXP 1.15M
*
* Temp Sensistive Offset IBias
I63 0 63 DC 1uA
R63 631 63 REXP2 .005
R631 0 631 2.25
*
* Models
.MODEL NMI NMOS(L=2.00U W=100U KP=20.0U LEVEL=1 )
.MODEL DESD D N=1 IS=1.00E-15
.MODEL DN1 D IS=1P KF=146E-18 AF=1
.MODEL REXP RES TCE= 7
.MODEL REXP2 RES TCE= 7
.ENDS MCP631

In message <6iHTSlOY3r8RFwLH@...>, dated Fri, 26 Jul 2013, John Woodgate <jmw@...> writes:

What i need is a way to define different elements of the line (segment
of cable, different types of branches) in order to have a database to
use to display the desired network topology and analyze the signal
behaviour through the line.

This can be an exceedingly complex matter. I think you need much more guidance from your tutor.

I found another Wikipedia page that specifically explains a-parameters:



You need to scroll down quite a bit.
--
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Why is the stapler always empty just when you want it?

John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK

In message <ksud7b+n6i9@...>, dated Fri, 26 Jul 2013, desi2209 <desi0985@...> writes:

What i need is a way to define different elements of the line (segment of cable, different types of branches) in order to have a database to use to display the desired network topology and analyze the signal behaviour through the line.

This can be an exceedingly complex matter. I think you need much more guidance from your tutor.

In your previous post you said:

I need to simulate the cable behaviour between 90 kHz and 150 kHz. For these reason I think is always cited the abcd matrix and no others.

How I have to go on if I choose to work with the a matrix?

Now you say 'a-matrix'. That is NOT the same as ABCD matrix, it's one specific example of the general concept.

My teacher said that it is possible to define a new component in ltspice with the required matrix but I didn't find no hint in the web about it.

It's a black box with four terminals. It has input voltage and current and output voltage and current; these are four variables. It also has a feedback path and a feed-forward path, but being passive, these have equal properties.

The a-matrix gives you two equations. The left sides are input and output quantities, while the right sides connect the four variables with these quantities, the coefficients being the elements of the 2 x 2 a-matrix.

You need to make one of these 'black boxes' for each cable type and length.

Does that help? I have to say that the a-matrix is, as far as I know, not often used.
--
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Why is the stapler always empty just when you want it?

John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK

i'm working with power line communication systems.
The articles explain the trasmission line theory for cable modelling, but then start to talk about abcd matrix and the advantage to describe the cable with this element, because on power line cable there are several branches and a complex topology to describe and the abcd matrix permitts to evaluate the total transfer function simply with matrix multiplications.

What i need is a way to define different elements of the line (segment of cable, different types of branches) in order to have a database to use to display the desired network topology and analyze the signal behaviour through the line.

Instead of a matrix representation, you can use the normal transmission
line that is built into LTspice. At those low frequencies, it should work
well.

So I'm wondering what sort of "cable" you need to model, and why an
ordinary transmission line isn't what those articles were using?

Andy

I need to simulate the cable behaviour between 90 kHz and 150 kHz. For these reason I think is always cited the abcd matrix and no others.

How I have to go on if I choose to work with the a matrix?
My teacher said that it is possible to define a new component in ltspice with the required matrix but I didn't find no hint in the web about it.

thank you,
desi

Hi Bob

I always highlight the wave form pane and
do a Ctrl S to save the settings.
This will always display what ever was selected.

But, the auto zooming is always there.
Seems you cant turn that off and have it stick.

Al D.

--


AC2CL

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can go through the human heart like that felt by the inventor as
he sees some creation of the brain unfolding to success...
Such emotions make a man forget food, sleep, friends, love, everything.

- Nikola Tesla