开云体育

--- In LTspice@..., Arnold Esper <arnold.esper@n...>
wrote:

Guten Tag,
was sind das für Fehler in LT-Spice? Gerechnet mit LT-Spice und

Winspice3.

Hallo Arnold,
hier kann fast keiner deutsch, deshalb macht es wenig Sinn die Frage
zus?tzlich in deutsch zu stellen.

what sort of errors is this in LT-Spice? The Schematic is computed

with LT-Spice

and Winspice3 from Mike Smith.
V1 1 0 DC 0 AC 1 PWL(0 0V 1m 0V 5m -.6V 13m +.8V 17m 0V)

I had the same problem some times ago with a model I think. The
problem here is that LTSPICE cannot interpret the '+' sign of a
number. So simply remove the '+' at the beginning of any number.
V1 1 0 DC 0 AC 1 PWL(0 0V 1m 0V 5m -.6V 13m .8V 17m 0V)

WINSPICE and PSPICE! have no problem with the '+' sign.

I didn't find any control to max Time Steps in
the .trans analysis.
.TRAN 10u 20m

You have to give four parameters if you want specify a maximum time
step. The command line could look in your example like this one.
.TRAN 10u 20m 0 10u
The other chance is a .option command line.
.TRAN 20m
.OPTIONS maxstep=10u


Hello Mike,
would it be difficult to improve your interpreter so that it
correctly accepts a '+' sign?

Best Regards
Helmut

Guten Tag,
was sind das fr Fehler in LT-Spice? Gerechnet mit LT-Spice und Winspice3.

Hello,
what sort of errors is this in LT-Spice? The Schematic is computed with LT-Spice
and Winspice3 from Mike Smith. I didn't find any control to max Time Steps in
the .trans analysis.

Arnold


BEGRE00 Begrenzer mit Transistoren


* *
* B E G R E N Z E R T R A N S I S T O R E N 0 0 . C I R *
* *
* Begrenzer mit Transistoren und Dioden in der Gegenkopplung *
* Benutzter OPA: TL 051 *
* *
* 20.03.2003 Arnold Esper *
* *



* *
* Definition der Eingangsspannung VIN zwischen Knoten 1 und 0 mit AC *
* und Puls, AC mit 1VOLT, der Puls wird festgelegt durch : *
* *
* PULS(U1 U2 T_VERZOEGER T_ANSTIEG T_ABFALL T_WEITE T_PERIODE) *
* *
* U2_|_ _ ______________ ____ *
* | / &#92; / *
* | / &#92; / *
* | / &#92; / *
* U1-|-------- - - - - - ------------------------ *
* | *
* *
* T_VERZ |T_AN| T_WEITE |T_AB| *
* | T_PERIODE | *
* *

* *
* Definition einer Polygonquelle (piece-wise-linear) *
* *
* PULS(U1 U2 T_VERZOEGER T_ANSTIEG T_ABFALL T_WEITE T_PERIODE) *
* *
* _|_ ______________ *
* | / &#92; *
* | / &#92; *
* | / &#92; *
* u0-|------- - - - - - &#92;- - - - - - - - - - *
* | &#92; *
* | &#92;____________________________ *
* *
* | | | | | *
* t0 u0 t1 u1 t2 u2 t3 u3 t4 u4 *
* *


*V1 1 0 DC 0 AC 1 PULSE(0 .6 100u 1m 1m 1n 1s)

**** Polygon-Quelle **

V1 1 0 DC 0 AC 1 PWL(0 0 1m 0V 5m -.6V 13m +.8V 17m 0V)



R1 1 2 22K
R2 2 4 22K
R3 4 6 100K
R4 6 7 22K
D1 2 3 DI
D2 7 5 DI
Q1 3 6 7 BC550C
Q2 5 4 2 BC550C
*E0 7 0 0 2 100K
X1 0 2 60 70 7 TL051/TI

* Betriebsspannungen VP VN ***

VP 60 0 DC 15
VN 70 0 DC -15

**** Analysen ****

*.OPTIONS LIMPTS=10000
*.AC DEC 100 10 20000
*.PRINT AC VDB(7)
.TRAN 10u 20m
.PRINT TRAN V(7)
*.DC V1 -1 1 0.001
*.PRINT DC V(7)


.model DI D



.model BC550C NPN(Is=7.049f Xti=3 Eg=1.11 Vaf=23.89 Bf=493.2 Ise=99.2f
+ Ne=1.829 Ikf=.1542 Xtb=1.5 Br=2.886 Isc=7.371p
+ Nc=1.508 Ikr=5.426 Rc=1.175 Cjc=5.5p Mjc=.3132 Vjc=.4924 Fc=.5
+ Cje=11.5p Mje=.6558 Vje=.5 Tr=10n Tf=420.3p Itf=1.374 Xtf=39.42
+ Vtf=10)
* PHILIPS pid=bc549c case=TO92
* 91-07-31 dsq

*
* TL051 operational amplifier "macromodel" subcircuit
* created using Parts release 4.01 on 04/12/89 at 09:57
* (REV N/A)
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
.subckt TL051/TI 1 2 3 4 5
*
c1 11 12 3.988E-12
c2 6 7 15.00E-12
dc 5 53 dx
de 54 5 dx
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0 2.875E6 -3E6 3E6 3E6 -3E6
ga 6 0 11 12 292.2E-6
gcm 0 6 10 99 6.542E-9
iss 3 10 dc 300.0E-6
hlim 90 0 vlim 1K
j1 11 2 10 jx
j2 12 1 10 jx
r2 6 9 100.0E3
rd1 4 11 3.422E3
rd2 4 12 3.422E3
ro1 8 5 125
ro2 7 99 125
rp 3 4 11.11E3
rss 10 99 666.7E3
vb 9 0 dc 0
vc 3 53 dc 3
ve 54 4 dc 3.700
vlim 7 8 dc 0
vlp 91 0 dc 28
vln 0 92 dc 28
.model dx D(Is=800.0E-18)
.model jx PJF(Is=15.00E-12 Beta=185.2E-6 Vto=-1)
.ends

*

.END

Sean,

See the examples called wavein.asc and waveout.asc in
the "educational" folder and also see help files for .wave

It is very cool indeed!

Brad


--- In LTspice@..., "sean_schouten" <sean_schouten@y...>
wrote:

Hi!

I too am new to spice. I heard that you were supposed to export a
output-waveform to a Wav-file somehow. Can any-one tell me how?

Would be cool.

Cheers, Sean

Hi!

I too am new to spice. I heard that you were supposed to export a
output-waveform to a Wav-file somehow. Can any-one tell me how?

Would be cool.

Cheers, Sean

Steve,

[...]Is this a fluke? Is there any way to tell if
a model will predict noise performance in general
and 1/f noise in particular.

I'm afraid it probably was, unless noise was
dominated by the resistors of your circuit.
Noise doesn't appear to be modeled in the LT2018A
macro model.

I think the only opamp macro model that claims to
model noise is the LT1028N.

--Mike

__________________________________________________
Do you Yahoo!?
Yahoo! Platinum - Watch CBS' NCAA March Madness, live on your desktop!

Thanks for the help on the Burr Brown amp.

Noise analysis is a nice feature of LTSpice. It's helpful to poke
around a circuit to see where noise is being generated. However, I
didn't put alot of credence into the actual predictions because of
potential limitations in the SPICE models.

Out of curosity, I compared the RMS noise in an actual circuit using
a couple of different op amps, including the LT2078A. I found that
the predicted noise was fairly close to the actual measured values.
The circuit is basically DC-coupled so 1/f noise is expected to be
significant.

Is this a fluke? Is there any way to tell if a model will predict
noise performance in general and 1/f noise in particular.

Steve H.

thanks Helmut, its running ok with models downloaded
from duncanamps.com
thanks a lot

guille

--- Helmut Sennewald <helmutsennewald@...>
wrote:

--- In LTspice@..., Bill Lewis
<wrljet@y...> wrote:

Please post any replies to this question to the

list.

I'm interested in vacuum tube modeling.

... and the obvious question: How do I relate the

previous info
with

the symbol.

Hello Bill,
you will find the symbol in the "misc" directory.
A short description follows:
1. Load the triode symbol into your schematic.
2. Replace the value 'triode' with the model name
used in the model
file. In this case it is '12AX7A'.
3. Put the model text into a file and store it in
your working
directory. That is the directory where your
schematic is.
4. Add the line .INCLUDE modelfilename in your
schematic.
That's it. This procedure will work for any kind of
part and you can
put as many models you want into one file.

It is important for any kind of symbol and model
that the pin order
is matching. Let's take a look to the triode symbol.
The provided
symbol has the pin order P(1), G(2), K(3). The model
text
uses .SUBCKT 12AX7A P G K . This means that P
is pin-1 G is pin-
2 and K is pin-3. We have luck, the pin order is the
same. If it is
different, then we could either change the order in
the model text or
in the symbol.

I have the ready to run example files attached.

By the way, the model isn't good at low Vpk
voltages. Take a look to
the Ip(Vgk, Vpk) plot to see what I mean.

Best Regards
Helmut




The model file: triode_12ax7a.sub
---------------------------------

* 12AX7A Triode PSpice Model 8/96, Rev. 1.0 (fp)
*
*

-------------------------------------------------------------------

* This model is provided "as is", with no warranty
of any kind,
* either expressed or implied, about the suitability
or fitness
* of this model for any particular purpose. Use of
this model
* shall be entirely at the user's own risk.
*
* For a discussion about vacuum tube modeling please
refer to:
* W. Marshall Leach, jr: "SPICE Models for
Vacuum-Tube Amplifiers";
* J. Audio Eng. Soc., Vol 43, No 3, March 1995.
*

-------------------------------------------------------------------

*
* This model is valid for the following tubes:
* 12AX7A/ECC83, 7025, 6EU7, 6681, 6AV6, 12DW7/7247
(Unit #1);
* at the following conditions:
* Plate voltage : 25..400V
* Grid voltage : 0..-3.5V
* Cathode current: 0..8mA
*
*
* Connections: Plate
* | Grid
* | | Cathode
* | | |
.SUBCKT 12AX7A P G K
E1 2 0 VALUE={45+V(P,K)+95.43*V(G,K)}
R1 2 0 1.0K
Gp P K
VALUE={1.147E-6*(PWR(V(2),1.5)+PWRS(V(2),1.5))/2}
Cgk G K 1.6P
Cgp G P 1.7P
Cpk P K 0.46P
.ENDS 12AX7A.SUBCKT 12AX7A P G K


The circuit file: triode_test.asc
---------------------------------

Version 4
SHEET 1 1104 692
WIRE 336 384 336 496
WIRE 368 288 368 224
WIRE 368 224 512 224
WIRE 512 336 512 224
WIRE 512 416 512 496
WIRE 512 496 336 496
WIRE 336 496 176 496
WIRE 176 496 176 448
WIRE 176 368 176 336
WIRE 176 336 320 336
WIRE 176 528 176 496
FLAG 176 528 0
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;Misc&#92;triode
368 336 R0
SYMATTR InstName U1
SYMATTR Value 12AX7A
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage 176
352 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage 512
320 R0
SYMATTR InstName V2
SYMATTR Value 200V
TEXT 142 136 Left 0 !;dc V2 0 200 0.1 V1 -5 20 5
TEXT 136 176 Left 0 !.INCLUDE triode_12ax7a.sub
TEXT 592 136 Left 0 ;.dc V2 0 200 0.1 V1 -5 20 5
Ip(Vpk, Vgk)
TEXT 144 96 Left 0 !.dc V1 -5 20 0.1
TEXT 592 96 Left 0 ;.dc V1 -5 20 0.1
Ip(Vgk)

__________________________________________________
Do you Yahoo!?
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Reinier,

Sounds interesting. Could you also
make a very simple opamp with the
output voltage limited to the
supply voltages? I sometimes get
Mega Volts in my circuit on 1 Volt
transients at the inputs.

Yes, the thing I have in mind would do
that. Below is a list prepared for
someone else who asked about this
offline:

I've in mind to model GBW, AOL, slew
limit, voltage and current noise and
corner frequencies for each(But not
model noise from input impedance
imbalance like from JFET input
products), dynamic current draw from
each rail, output voltage range,
output current limit, and input bias
current. That can all be modeled in
the modeling methodology used in the
SMPS products one one internal node.
Doing the real small signal transfer
above the dominate pole requires
more nodes. For example, the LT1028
can be done with two more nodes.
CMRR would not be particularly
modeled, but it would be non-zero.

--Mike

__________________________________________________
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--- In LTspice@..., "Helmut Sennewald"
<helmutsennewald@y...> wrote:

--- In LTspice@..., "kaplounovski" <kaplounovski@y...>
wrote:

--- In LTspice@..., Jim Stockton <mstech@p...> wrote:

kaplounovski wrote:

Hello,
I'm trying to use the National LMC6484A opamp model in

LTSpice.

I've downloaded their model and placed it
into ..&#92;LTC&#92;SWCADIII&#92;lib&#92;sub directory under the name

LMC6484A.sub.

Then I created a simple test schematic where I used opamp2

symbol

with

Prefix = X, Spice Model = LMC6484A.sub, Value = LMC6484A.sub
properties.
I've also added the .inc LMC6484A.sub directive to the

netlist.

Running the simulation produces the following error message:
Error: Unknown subckt called in: xu1 ...... lmc6484a.sub lmc

6484a.sub

What am I doing wrong?

Thanks,
Eugene.


To unsubscribe from this group, send an email to:
LTspice-unsubscribe@...



Your use of Yahoo! Groups is subject to

Try leaving model blank and using value = lmc6484a without

the .sub

Good Luck
Jim Stockton

Thank you, Jim.
I tried that, with the same outcome. This is how it was done in

the

old DOS-based PSpice, it worked there. I'm almost sure it's

something

really simple, like missing path or something, but what? Could it

be

that the op-amp's subcircuit in turn includes some models, namely
MOSFET, that LTSpice could not find?
Regards,
Eugene

Hello Eugene,
this is one of the two chances to include your moddel.
You can see the other one in the thread about the OPA336.
Sorry for my short explanations. I must immediately leave my home

to

go work.

Put the symbol file into the LTSPICE lib&#92;sym&#92;opamp directory.
Put the model file National.lib into LTSPICE lib&#92;sub directory.

Best Regards
Helmut


Test circuit file

Version 4
SHEET 1 1372 1316
WIRE 320 320 320 352
WIRE 320 256 320 224
WIRE -16 368 -16 304
WIRE -16 96 80 96
WIRE 80 304 -16 304
WIRE 160 304 240 304
WIRE 160 96 240 96
WIRE 288 272 240 272
WIRE 240 272 240 96
WIRE 464 96 512 96
WIRE 512 96 512 288
WIRE 512 288 352 288
WIRE -16 480 -16 448
WIRE 240 480 240 512
WIRE 384 480 384 512
WIRE 240 592 240 624
WIRE 384 592 384 624
WIRE 512 288 544 288
WIRE 240 96 384 96
WIRE 240 304 288 304
WIRE 320 976 320 1008
WIRE 320 912 320 880
WIRE -16 752 96 752
WIRE 80 960 -16 960
WIRE 160 960 240 960
WIRE 160 752 240 752
WIRE 288 928 240 928
WIRE 240 928 240 752
WIRE 464 752 512 752
WIRE 512 752 512 944
WIRE 512 944 352 944
WIRE 512 944 544 944
WIRE 240 752 384 752
WIRE 240 960 288 960
WIRE -16 1024 -16 960
WIRE -16 1136 -16 1104
FLAG 320 224 Vcc
FLAG 240 480 Vcc
FLAG 384 480 Vss
FLAG 320 352 Vss
FLAG -16 480 0
FLAG 240 624 0
FLAG 384 624 0
FLAG 544 288 out
FLAG 240 96 in-
FLAG 240 304 in+
FLAG -16 96 0
FLAG 320 880 Vcc
FLAG 320 1008 Vss
FLAG 544 944 out1
FLAG 240 752 in1-
FLAG 240 960 in1+
FLAG -16 752 0
FLAG -16 304 in
FLAG -16 1136 0
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage 240 496 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage 384 496 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage -16 352 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V3
SYMATTR Value 1
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;res 368 112 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 1MEG
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;res 64 320 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R2
SYMATTR Value 1MEG
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;res 64 112 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R3
SYMATTR Value 1MEG
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;res 368 768 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R4
SYMATTR Value 1MEG
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;res 64 976 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R5
SYMATTR Value 1
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;cap 96 768 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage -16 1008 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V4
SYMATTR Value 0
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;Opamps&#92;LMC6484A 320 224 R0
SYMATTR InstName U1
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;Opamps&#92;LMC6484A 320 880 R0
SYMATTR InstName U2
TEXT -432 40 Left 0 ;.op
TEXT -440 -160 Left 0 !.AC DEC 100 1 100MEG
TEXT -432 -40 Left 0 ;.nodeset V(out)=2 V(in-)=1 V(in+)=1
TEXT -432 -8 Left 0 ;.nodeset V(out1)=0 V(in1-)=0 V(in1+)=0
TEXT -432 -88 Left 0 ;.OPTIONS gmin=1e-10 noopiter=1


Symbol file LMC6484AA.asy

Version 4
SymbolType CELL
LINE Normal -32 32 32 64
LINE Normal -32 96 32 64
LINE Normal -32 32 -32 96
LINE Normal -28 48 -20 48
LINE Normal -28 80 -20 80
LINE Normal -24 84 -24 76
LINE Normal 0 32 0 48
LINE Normal 0 96 0 80
LINE Normal 4 44 12 44
LINE Normal 8 40 8 48
LINE Normal 4 84 12 84
WINDOW 0 16 32 Left 0
WINDOW 3 16 96 Left 0
SYMATTR Value LMC6484A/NS
SYMATTR Prefix X
SYMATTR SpiceModel National.lib
SYMATTR Value2 LMC6484A/NS
SYMATTR Description CMOS Operational Amplifier
PIN -32 80 NONE 0
PINATTR PinName In+
PINATTR SpiceOrder 1
PIN -32 48 NONE 0
PINATTR PinName In-
PINATTR SpiceOrder 2
PIN 0 32 NONE 0
PINATTR PinName V+
PINATTR SpiceOrder 3
PIN 0 96 NONE 0
PINATTR PinName V-
PINATTR SpiceOrder 4
PIN 32 64 NONE 0
PINATTR PinName OUT
PINATTR SpiceOrder 5




File national.lib

* National Semiconductor, Inc.

*/////////////////////////////////////////////////////////////////////

* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal

*////////////////////////////////////////////////////////////////////

* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@g...

*//////////////////////////////////////////////////////////
*LMC6484A CMOS Quad OP-AMP MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LMC6484A/NS 1 2 99 50 40
* CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS
CURRENT.
*
*Features:
*Operates from single or dual supplies
*Rail-to-rail input and output swing
*Ultra low input current = 10fA
*Slew rate = 1.2V/uS
*
*NOTE: Model is for single device only and simulated
* supply current is 1/4 of total device current.
* Noise is not modeled.
* Asymmetrical gain is not modeled.
*
**INPUT STAGE****
*
I1 99 4 17U
M1 5 2 4 99 MOSFET
R3 5 50 5.651K
M2 6 7 4 99 MOSFET
R4 6 50 5.651K
*Fp2=5.9 MHz
C4 5 6 2.3868P
G0 98 9 6 5 4.4165E-2
R0 98 9 1K
DP1 1 99 DA
DP2 50 1 DB
DP3 2 99 DB
DP4 50 2 DA
*For accurate Ib , set GMIN<=1E-16 on .OPTIONS line.
*
*COMMON MODE EFFECT*
*
I2 99 50 420.5U
*^Quiescent current
EOS 7 1 POLY(1) 16 49 .75E-3 1
*Offset voltage..........^
R8 99 49 40K
R9 49 50 40K
*
POLE STAGE
*
*Fp=13.3 MHz
G3 98 15 9 49 1E-3
R12 98 15 1K
C5 98 15 11.967P
*
**POLE/ZERO STAGE***
*
*Fp=600 KHz, Fz= 1.4MHz
G5 98 18 15 49 1E-3
R14 98 18 1K
R15 98 19 750
C6 19 18 151.58P
*
****COMMON-MODE ZERO STAGE****
*
*Fpcm=20 KHz
G4 98 16 POLY(2) 1 49 2 49 0 2.812E-8 2.812E-8
L2 98 17 7.958M
R13 17 16 1K
*
****SECOND STAGE****
*
EH 99 98 99 49 1
G1 98 29 18 49 5.6667E-6
R5 98 29 100.37MEG
V2 99 8 1.56
D1 29 8 DX
D2 10 29 DX
V3 10 50 1.56
*
****OUTPUT STAGE****
*
F6 99 50 VA7 1
*^Dynamic supply current
F5 99 35 VA8 1
D3 36 35 DX
VA7 99 36 0
D4 35 99 DX
E1 99 37 99 49 1
VA8 37 38 0
G6 38 40 49 29 16.667E-3
R16 38 40 2.3886K
V4 30 40 .77
D5 30 99 DX
V5 40 31 .77
D6 50 31 DX
*Fp1=2.343 Hz
C3 29 39 17P
R6 39 40 1K
*
MODELS USED****
*
.MODEL DA D(IS=2E-14)
.MODEL DB D(IS=1E-14)
.MODEL DX D(IS=1E-14)
.MODEL MOSFET PMOS(VTO=0 KP=1.842E-3)
.ENDS
*$

Thank you Helmut!
It works now, although when I used your model, I got the "Too few
nodes: current" message. I did not use your example file because of
the different file structure (paths) on my computer. All worked well
though with the model I downloaded from the National site yesterday.
Now I guess I know where my error was - I tried to use a ready symbol
from the library whereas I should have created my own for each 'new'
part I want to use.
Best regards,
Eugene

--- In LTspice@..., "kaplounovski" <kaplounovski@y...>
wrote:

--- In LTspice@..., Jim Stockton <mstech@p...> wrote:

kaplounovski wrote:

Hello,
I'm trying to use the National LMC6484A opamp model in LTSpice.
I've downloaded their model and placed it
into ..&#92;LTC&#92;SWCADIII&#92;lib&#92;sub directory under the name

LMC6484A.sub.

Then I created a simple test schematic where I used opamp2

symbol

with

Prefix = X, Spice Model = LMC6484A.sub, Value = LMC6484A.sub
properties.
I've also added the .inc LMC6484A.sub directive to the netlist.

Running the simulation produces the following error message:
Error: Unknown subckt called in: xu1 ...... lmc6484a.sub lmc

6484a.sub

What am I doing wrong?

Thanks,
Eugene.


To unsubscribe from this group, send an email to:
LTspice-unsubscribe@...



Your use of Yahoo! Groups is subject to

Try leaving model blank and using value = lmc6484a without

the .sub

Good Luck
Jim Stockton

Thank you, Jim.
I tried that, with the same outcome. This is how it was done in the
old DOS-based PSpice, it worked there. I'm almost sure it's

something

really simple, like missing path or something, but what? Could it

be

that the op-amp's subcircuit in turn includes some models, namely
MOSFET, that LTSpice could not find?
Regards,
Eugene

Hello Eugene,
this is one of the two chances to include your moddel.
You can see the other one in the thread about the OPA336.
Sorry for my short explanations. I must immediately leave my home to
go work.

Put the symbol file into the LTSPICE lib&#92;sym&#92;opamp directory.
Put the model file National.lib into LTSPICE lib&#92;sub directory.

Best Regards
Helmut


Test circuit file

Version 4
SHEET 1 1372 1316
WIRE 320 320 320 352
WIRE 320 256 320 224
WIRE -16 368 -16 304
WIRE -16 96 80 96
WIRE 80 304 -16 304
WIRE 160 304 240 304
WIRE 160 96 240 96
WIRE 288 272 240 272
WIRE 240 272 240 96
WIRE 464 96 512 96
WIRE 512 96 512 288
WIRE 512 288 352 288
WIRE -16 480 -16 448
WIRE 240 480 240 512
WIRE 384 480 384 512
WIRE 240 592 240 624
WIRE 384 592 384 624
WIRE 512 288 544 288
WIRE 240 96 384 96
WIRE 240 304 288 304
WIRE 320 976 320 1008
WIRE 320 912 320 880
WIRE -16 752 96 752
WIRE 80 960 -16 960
WIRE 160 960 240 960
WIRE 160 752 240 752
WIRE 288 928 240 928
WIRE 240 928 240 752
WIRE 464 752 512 752
WIRE 512 752 512 944
WIRE 512 944 352 944
WIRE 512 944 544 944
WIRE 240 752 384 752
WIRE 240 960 288 960
WIRE -16 1024 -16 960
WIRE -16 1136 -16 1104
FLAG 320 224 Vcc
FLAG 240 480 Vcc
FLAG 384 480 Vss
FLAG 320 352 Vss
FLAG -16 480 0
FLAG 240 624 0
FLAG 384 624 0
FLAG 544 288 out
FLAG 240 96 in-
FLAG 240 304 in+
FLAG -16 96 0
FLAG 320 880 Vcc
FLAG 320 1008 Vss
FLAG 544 944 out1
FLAG 240 752 in1-
FLAG 240 960 in1+
FLAG -16 752 0
FLAG -16 304 in
FLAG -16 1136 0
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage 240 496 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage 384 496 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage -16 352 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V3
SYMATTR Value 1
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;res 368 112 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 1MEG
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;res 64 320 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R2
SYMATTR Value 1MEG
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;res 64 112 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R3
SYMATTR Value 1MEG
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;res 368 768 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R4
SYMATTR Value 1MEG
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;res 64 976 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R5
SYMATTR Value 1
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;cap 96 768 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage -16 1008 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V4
SYMATTR Value 0
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;Opamps&#92;LMC6484A 320 224 R0
SYMATTR InstName U1
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;Opamps&#92;LMC6484A 320 880 R0
SYMATTR InstName U2
TEXT -432 40 Left 0 ;.op
TEXT -440 -160 Left 0 !.AC DEC 100 1 100MEG
TEXT -432 -40 Left 0 ;.nodeset V(out)=2 V(in-)=1 V(in+)=1
TEXT -432 -8 Left 0 ;.nodeset V(out1)=0 V(in1-)=0 V(in1+)=0
TEXT -432 -88 Left 0 ;.OPTIONS gmin=1e-10 noopiter=1


Symbol file LMC6484AA.asy

Version 4
SymbolType CELL
LINE Normal -32 32 32 64
LINE Normal -32 96 32 64
LINE Normal -32 32 -32 96
LINE Normal -28 48 -20 48
LINE Normal -28 80 -20 80
LINE Normal -24 84 -24 76
LINE Normal 0 32 0 48
LINE Normal 0 96 0 80
LINE Normal 4 44 12 44
LINE Normal 8 40 8 48
LINE Normal 4 84 12 84
WINDOW 0 16 32 Left 0
WINDOW 3 16 96 Left 0
SYMATTR Value LMC6484A/NS
SYMATTR Prefix X
SYMATTR SpiceModel National.lib
SYMATTR Value2 LMC6484A/NS
SYMATTR Description CMOS Operational Amplifier
PIN -32 80 NONE 0
PINATTR PinName In+
PINATTR SpiceOrder 1
PIN -32 48 NONE 0
PINATTR PinName In-
PINATTR SpiceOrder 2
PIN 0 32 NONE 0
PINATTR PinName V+
PINATTR SpiceOrder 3
PIN 0 96 NONE 0
PINATTR PinName V-
PINATTR SpiceOrder 4
PIN 32 64 NONE 0
PINATTR PinName OUT
PINATTR SpiceOrder 5




File national.lib

* National Semiconductor, Inc.

*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal

*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@...

*//////////////////////////////////////////////////////////
*LMC6484A CMOS Quad OP-AMP MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LMC6484A/NS 1 2 99 50 40
* CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS
CURRENT.
*
*Features:
*Operates from single or dual supplies
*Rail-to-rail input and output swing
*Ultra low input current = 10fA
*Slew rate = 1.2V/uS
*
*NOTE: Model is for single device only and simulated
* supply current is 1/4 of total device current.
* Noise is not modeled.
* Asymmetrical gain is not modeled.
*
**INPUT STAGE****
*
I1 99 4 17U
M1 5 2 4 99 MOSFET
R3 5 50 5.651K
M2 6 7 4 99 MOSFET
R4 6 50 5.651K
*Fp2=5.9 MHz
C4 5 6 2.3868P
G0 98 9 6 5 4.4165E-2
R0 98 9 1K
DP1 1 99 DA
DP2 50 1 DB
DP3 2 99 DB
DP4 50 2 DA
*For accurate Ib , set GMIN<=1E-16 on .OPTIONS line.
*
*COMMON MODE EFFECT*
*
I2 99 50 420.5U
*^Quiescent current
EOS 7 1 POLY(1) 16 49 .75E-3 1
*Offset voltage..........^
R8 99 49 40K
R9 49 50 40K
*
POLE STAGE
*
*Fp=13.3 MHz
G3 98 15 9 49 1E-3
R12 98 15 1K
C5 98 15 11.967P
*
**POLE/ZERO STAGE***
*
*Fp=600 KHz, Fz= 1.4MHz
G5 98 18 15 49 1E-3
R14 98 18 1K
R15 98 19 750
C6 19 18 151.58P
*
****COMMON-MODE ZERO STAGE****
*
*Fpcm=20 KHz
G4 98 16 POLY(2) 1 49 2 49 0 2.812E-8 2.812E-8
L2 98 17 7.958M
R13 17 16 1K
*
****SECOND STAGE****
*
EH 99 98 99 49 1
G1 98 29 18 49 5.6667E-6
R5 98 29 100.37MEG
V2 99 8 1.56
D1 29 8 DX
D2 10 29 DX
V3 10 50 1.56
*
****OUTPUT STAGE****
*
F6 99 50 VA7 1
*^Dynamic supply current
F5 99 35 VA8 1
D3 36 35 DX
VA7 99 36 0
D4 35 99 DX
E1 99 37 99 49 1
VA8 37 38 0
G6 38 40 49 29 16.667E-3
R16 38 40 2.3886K
V4 30 40 .77
D5 30 99 DX
V5 40 31 .77
D6 50 31 DX
*Fp1=2.343 Hz
C3 29 39 17P
R6 39 40 1K
*
MODELS USED****
*
.MODEL DA D(IS=2E-14)
.MODEL DB D(IS=1E-14)
.MODEL DX D(IS=1E-14)
.MODEL MOSFET PMOS(VTO=0 KP=1.842E-3)
.ENDS
*$

--- In LTspice@..., Jim Stockton <mstech@p...> wrote:

kaplounovski wrote:

Hello,
I'm trying to use the National LMC6484A opamp model in LTSpice.
I've downloaded their model and placed it
into ..&#92;LTC&#92;SWCADIII&#92;lib&#92;sub directory under the name

LMC6484A.sub.

Then I created a simple test schematic where I used opamp2 symbol

with

Prefix = X, Spice Model = LMC6484A.sub, Value = LMC6484A.sub
properties.
I've also added the .inc LMC6484A.sub directive to the netlist.

Running the simulation produces the following error message:
Error: Unknown subckt called in: xu1 ...... lmc6484a.sub lmc

6484a.sub

What am I doing wrong?

Thanks,
Eugene.


To unsubscribe from this group, send an email to:
LTspice-unsubscribe@...



Your use of Yahoo! Groups is subject to

Try leaving model blank and using value = lmc6484a without the .sub
Good Luck
Jim Stockton

Thank you, Jim.
I tried that, with the same outcome. This is how it was done in the
old DOS-based PSpice, it worked there. I'm almost sure it's something
really simple, like missing path or something, but what? Could it be
that the op-amp's subcircuit in turn includes some models, namely
MOSFET, that LTSpice could not find?
Regards,
Eugene

Andre,

makes me wonder if there is any way to start a
transient simulation, stop at some predefined
point in time and use that result for the ac
simulation.

No this isn't possible in LTspice. It's pretty
hard to implement. What you can do, to help
with your confidence in the solution from a .ac
analysis, is to do a .step set of runs that
varies some aspect of the dc operating point
and see if the .ac small signal transfer function
looks the same for all those slightly different
.op points.

I had that problem too, but in my
designs i almost only rely on transient
simulation (for the exact same reason that you
mentioned above and because large signals
change the operating point anyways).

Yes, e.g., power amplifier stability is really
difficult to do reliably in small signal .ac
analysis. The open loop gain/phase varies
wildly with output stage operating point.
One method that helps in this situation is to
drive the amp to one end or the other with a DC
input source and insert a floating AC source
in the loop in front of a high impedance
point for an .ac analysis. The open
loop transfer function can be obtained from
the ratio of voltages to either side of the
floating source.

But ultimately, the .tran analysis comes
out at the ultimate SPICE test of stability.

Best Regards,

--Mike

__________________________________________________
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Hi Mike,

Helmut,

[...]I have read in a book? that .TRAN analysis
always does converge better.

Hello Mike, is that true?[...]

The .tran solution is always more believable
than the .op solution. SPICE programs are
prone to "false convergence", a numerical
situation in which the error-based checks
accept an answer which is nonsense. This
can happen once and through off a .op
solution, but it *rarely* will happen
repeatably in the .tran solution.

The .ac solution is thereby somewhat suspect
because it is based solely on the .op solution.

But as far as better convergence with respect
to giving up due to convergence errors(not
counting accepting false answers), the .tran
has only one advantage, it can start simulation
without a .op solution while the .ac cannot.
But normally both need the .op solution.
For the .ac analysis, there is basically
no further possibility of convergence failures
after the .op, because everything after that
is an exact solution of the linearized circuit.

--Mike

makes me wonder if there is any way to start a transient simulation,
stop at some predefined point in time and use that result for the ac
simulation. I had that problem too, but in my designs i almost only
rely on transient simulation (for the exact same reason that you
mentioned above and because large signals change the operating point
anyways).

Andre

the latest revision 2.01o now runs my test circuit
for the OPA336 without the 'gmin' hack, but the
line .OPTIONS gmin=1e-10 noopiter=1
is still necessary.

Yes, I was able to reduce gmin to 1e-11, though.

Was this change coming from the missed JFET
parameter?

Apparently so, now the MOSFET's leak more. BTW,
the model, since it uses current sources, should
probably be run with the "Add GMIN across current
sources" hack because the model was written for
PSpice.

From the notes written in the model, it looks
like PSpice had a hard time with it, too.

BTW, I'm thinking of introducing opamp models that
use a different modeling methodology, similar to
that used for LTspice's SMPS products. The result
would be computationally extremely lightweight and
robust models that model noise too(these PSpice-
style opamp models almost never get the noise
modeled). However, the opamps models would not
run in other SPICE simulators and non-LT opamp
models wouldn't be available. Would you folks be
interested in something like that?

--Mike

__________________________________________________
Do you Yahoo!?
Yahoo! Platinum - Watch CBS' NCAA March Madness, live on your desktop!

--- In LTspice@..., Panama Mike <panamatex@y...> wrote:

Helmut,

[...]I have read in a book? that .TRAN analysis
always does converge better.

Hello Mike, is that true?[...]

The .tran solution is always more believable
than the .op solution. SPICE programs are
prone to "false convergence", a numerical
situation in which the error-based checks
accept an answer which is nonsense. This
can happen once and through off a .op
solution, but it *rarely* will happen
repeatably in the .tran solution.

The .ac solution is thereby somewhat suspect
because it is based solely on the .op solution.

But as far as better convergence with respect
to giving up due to convergence errors(not
counting accepting false answers), the .tran
has only one advantage, it can start simulation
without a .op solution while the .ac cannot.
But normally both need the .op solution.
For the .ac analysis, there is basically
no further possibility of convergence failures
after the .op, because everything after that
is an exact solution of the linearized circuit.

Hello Mike,
the latest revision 2.01o now runs my test circuit for the OPA336
without the 'gmin' hack, but the line
.OPTIONS gmin=1e-10 noopiter=1
is still necessary.

Was this change coming from the missed JFET parameter?

Best Regards
Helmut

I wrote:

[...] I suggest either removing and asking
TI/Burr-Brown why the error is in the model.

but meant:

[...] I suggest either removing vfb=... from
the models or just ignoring the error message
and then asking TI/Burr-Brown why the error is
in the model.

--Mike

__________________________________________________
Do you Yahoo!?
Yahoo! Platinum - Watch CBS' NCAA March Madness, live on your desktop!

Helmut,

[...]I have read in a book? that .TRAN analysis
always does converge better.

Hello Mike, is that true?[...]

The .tran solution is always more believable
than the .op solution. SPICE programs are
prone to "false convergence", a numerical
situation in which the error-based checks
accept an answer which is nonsense. This
can happen once and through off a .op
solution, but it *rarely* will happen
repeatably in the .tran solution.

The .ac solution is thereby somewhat suspect
because it is based solely on the .op solution.

But as far as better convergence with respect
to giving up due to convergence errors(not
counting accepting false answers), the .tran
has only one advantage, it can start simulation
without a .op solution while the .ac cannot.
But normally both need the .op solution.
For the .ac analysis, there is basically
no further possibility of convergence failures
after the .op, because everything after that
is an exact solution of the linearized circuit.

--Mike

__________________________________________________
Do you Yahoo!?
Yahoo! Platinum - Watch CBS' NCAA March Madness, live on your desktop!

Steve,

I am trying to run a Burr Brown Op Amp, the
OPA336. The transient analysis "sort of"
runs but LTSpice notes a couple of problems,
most notably unrecognized parameters, jssw
and vfb.

I couldn't find this model. Can you send it to me.

Here's the link to the TI page. Thanks

genericPartNumber=OPA336&pfsection=models

Thanks for the link. OK, here's the story.
Jssw is a perimeter-based bulk leakage current
parameter. The MOSFET models in the the macro
model are written such that the bulk leakage is
dominated by the source and drain perimeters,
not that I think that has much to do with the
overall behavior of the macromodel.

I have implemented jssw in LTspice and it is
now available now as version 2.01o. Thank
you very much for the test case that pointed it
out that jssw was missing.

However, Vfb is not a level 3 MOSFET parameter.
PSpice accepts it, but does apparently nothing
with it. LTspice will still complain, which is
okay I think because it is an error in the
model. I suggest either removing and asking
TI/Burr-Brown why the error is in the model.

--Mike

__________________________________________________
Do you Yahoo!?
Yahoo! Platinum - Watch CBS' NCAA March Madness, live on your desktop!

--- In LTspice@..., "polapart" <sahawley@m...> wrote:

--- polapart <sahawley@m...> wrote:

I am trying to run a Burr Brown Op Amp, the OPA336.
The transient analysis "sort of" runs but LTSpice
notes a couple of problems, most notably
unrecognized parameters, jssw and vfb.

I couldn't find this model. Can you send it to me.

--Mike

Here's the link to the TI page. Thanks

genericPartNumber=OPA336&pfsection=models

Hello Steve,
the magic trick for the convergence problem in .AC analysis is the
latest 'gnin parallel current source' feature.
That was the only way I found to get convergence in .AC analysis for
this OPAMP.

Enable this feature in the control panel.
Control Panel->Hacks-> Add GMIN across current sorce
But this alone doesn't help. We have to add the command line
.OPTIONS gmin=1e-10 noopiter=1 into the schematic.

I have read in a book? that .TRAN analysis always does converge
better.

Hello Mike,
is that true?
Unfortunately this doesn't help anything when somebody has to make
a .AC analysis.

What's about this error message regarding JFET parameters?
Error on line 61 : .model nch nmos (level=3 tox=30e-9 cgdo=1.55e-10
cgso=1.55e-10 cj=6.300e-4 cjsw=3.83e-10 af=1.05 kf=2.6e-31 js=2.0e-7
jssw=5e-13 rsh=68 mj=.25 mjsw=.11 vfb=-0.784 phi=0.792 vto=.81 ld=34e-
9 wd=17e-9 tpg=-1 gamma=0.6)
Unrecognized parameter "jssw" - ignored
Unrecognized parameter "vfb" - ignored
Error on line 60 : .model pch pmos (level=3 tox=30e-9 cgdo=1.80e-10
cgso=1.80e-10 cj=7.199e-4 cjsw=3.40e-10 af=1.05 kf=1.0e-31 js=4.0e-7
jssw=3.0e-13 rsh=117 mj=.47 mjsw=.16 vfb=-0.34 phi=0.71 vto=-.892
ld=12e-9 wd=43e-9 tpg=+1 gamma=0.6)
Unrecognized parameter "jssw" - ignored
Unrecognized parameter "vfb" - ignored

I have my test files attached.

Best Regards
Helmut

The LTSPICE file for .AC analysis.

Version 4
SHEET 1 1372 1316
WIRE 320 320 320 352
WIRE 320 256 320 224
WIRE -16 368 -16 304
WIRE -16 96 80 96
WIRE 80 304 -16 304
WIRE 160 304 240 304
WIRE 160 96 240 96
WIRE 288 272 240 272
WIRE 240 272 240 96
WIRE 464 96 512 96
WIRE 512 96 512 288
WIRE 512 288 352 288
WIRE -16 480 -16 448
WIRE 240 480 240 512
WIRE 384 480 384 512
WIRE 240 592 240 624
WIRE 384 592 384 624
WIRE 512 288 544 288
WIRE 240 96 384 96
WIRE 240 304 288 304
WIRE 320 976 320 1008
WIRE 320 912 320 880
WIRE -16 752 96 752
WIRE 80 960 -16 960
WIRE 160 960 240 960
WIRE 160 752 240 752
WIRE 288 928 240 928
WIRE 240 928 240 752
WIRE 464 752 512 752
WIRE 512 752 512 944
WIRE 512 944 352 944
WIRE 512 944 544 944
WIRE 240 752 384 752
WIRE 240 960 288 960
WIRE -16 1024 -16 960
WIRE -16 1136 -16 1104
FLAG 320 224 Vcc
FLAG 240 480 Vcc
FLAG 384 480 Vss
FLAG 320 352 Vss
FLAG -16 480 0
FLAG 240 624 0
FLAG 384 624 0
FLAG 544 288 out
FLAG 240 96 in-
FLAG 240 304 in+
FLAG -16 96 0
FLAG 320 880 Vcc
FLAG 320 1008 Vss
FLAG 544 944 out1
FLAG 240 752 in1-
FLAG 240 960 in1+
FLAG -16 752 0
FLAG -16 304 in
FLAG -16 1136 0
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;x_models&#92;xopamp 320 224 R0
SYMATTR InstName U1
SYMATTR Value OPA336
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage 240 496 R0
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage 384 496 R0
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage -16 352 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V3
SYMATTR Value 1
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;res 368 112 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 1MEG
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;res 64 320 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R2
SYMATTR Value 1MEG
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;res 64 112 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R3
SYMATTR Value 1MEG
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;x_models&#92;xopamp 320 880 R0
SYMATTR InstName U2
SYMATTR Value OPA336
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;res 368 768 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R4
SYMATTR Value 1MEG
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;res 64 976 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R5
SYMATTR Value 1
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;cap 96 768 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage -16 1008 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V4
SYMATTR Value 0
TEXT -432 40 Left 0 ;.op
TEXT -432 -128 Left 0 !.include opa336.mod
TEXT -440 -160 Left 0 !.AC DEC 100 1 100MEG
TEXT -432 -40 Left 0 !.nodeset V(out)=2 V(in-)=1 V(in+)=1
TEXT -400 1256 Left 0 ;.OPTIONS vntol=1e-2 reltol=1e-2 itl1=500
itl2=500 itl6=500 abstol=1e-4 gmin=1e-9 gminsteps=100 noopiter=1
pivtol=1e-6
TEXT -432 -8 Left 0 !.nodeset V(out1)=0 V(in1-)=0 V(in1+)=0
TEXT -432 -88 Left 0 !.OPTIONS gmin=1e-10 noopiter=1
TEXT -400 1288 Left 0 ;.OPTIONS itl1=500 itl2=500 itl6=500 vntol=1e-
3 abstol=1e-12 reltol=1e-3 trtol=1 pivtol=1e-13 pivrel=1e-3 gmin=1e-
12 gminsteps=100 noopiter=1







The model OPA336.mod:
Be carefully with the broken lines I see in this awful YAHOO-editor.


* -------------------------------------------------------------------
-----
* | NOTICE: THE INFORMATION PROVIDED HEREIN IS BELIEVED TO BE
RELIABLE; |
* | HOWEVER; BURR-BROWN ASSUMES NO RESPONSIBILITY FOR INACCURACIES
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* -------------------------------------------------------------------
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*
*
*
* SUBCIRCUIT MACROMODEL OPA336
* PSpice ver. 6.3
* REV A. CREATED Wednesday, June 18, 1997 RH
* REV B. 25 JUNE 97 NPA: COMPILED INTO OPA336.MOD
* REV C. 26 JUNE 97 NPA: EDITED NODE SYNTAX AND ADDED .OPTION NOTES
*
* Notes concerning using macromodel to simulate OPA336:
* 1) Model is actually a simplified schematic of OPA336.
* 2) Model was created with PSpice ver. 6.3, level 3 device models.
* 3) Operation of the circuit is assumed to be single supply
*

* Example: X_U1 1 2 3 0 5 OPA336
*

* Where U is the subcircuit name and
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* .subckt OPA336 1 2 3 4 5
*
* Note that node "4" may be connected to ground "0", i.e., single
supply operation.
*
* 4) ADD .OPTION ITL=40 AND .OPTION GMIN=10p TO NET LIST IF
SIMULATION DOES NOT
* CONVERGE
* 5) ADDING .NODESET STATEMENT (BELOW) TO NET LIST MAY HELP
CONVERGENCE IS CASES
* WHERE V+=5V AND V-=0V ; SINGLE SUPPLY OPERATION. ASSUMES
SUBCIRCUIT IS "U1".
*
* .NODESET
* +V(2) = 2.5 V(1) = 2.5 V(5) = 2.5 V(3) = 5.0
* +V(X_U1.20)= 3.8 V(X_U1.23)= 3.8 V(X_U1.25)= .834 V(X_U1.27)
= .833 V(X_U1.29)= .834
* +V(X_U1.32)= 2.03 V(X_U1.34)= 2.03 V(X_U1.43)= 4.065 V(X_U1.44)=
2.51 V(X_U1.45)= 1.93
* +V(X_U1.47)= 1.93 V(X_U1.51)= .848 V(X_U1.53)= 4.07 V(X_U1.54)=
1.58 V(X_U1.55)= 4.02
* +V(X_U1.60)= 1.94 V(X_U1.62)= .855 V(X_U1.64)= 3.17 V(X_U1.67)=
4.98 V(X_U1.76)= 2.51
* +V(X_U1.GNDS)= 0.0 V(0)= 0.0
*
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
.subckt OPA336 1 2 3 4 5
*
M61 4 64 55 55 PCH W=20U L=0.8U M=1
M59 55 53 3 3 PCH W=15U L=5U M=4
M55 55 60 51 GNDS NCH W=5U L=0.8U M=1
M53 53 45 51 GNDS NCH W=5U L=0.8U M=1
M57 53 53 3 3 PCH W=15U L=5U M=2
C55 55 60 CP1P2 2P
M67 55 55 67 3 PCH W=5U L=5U M=1
M74 45 51 62 GNDS NCH W=5U L=1U M=1
R67 3 67 RNW 200K
R47 45 47 RPO2 2K
ITAIL 3 23 DC 6U AC 0
ITAIL2 27 4 DC 1.6U AC 0
ITAIL3 51 4 DC 0.8U AC 0
I60 3 60 DC 0.4U AC 0
RGNDS GNDS 4 0.01
M24 29 1 23 3 PCH W=90U L=2U AD=2560P PD=3328U AS=2688P
PS=3494U M=1
M26 29 27 4 GNDS NCH W=500U L=2U AD=1142P PD=1670U AS=1142P
PS=1670U M=1
I20 20 4 DC 1U AC 0
R20 3 20 1.2MEG
M20 4 20 23 3 PCH W=5U L=2U M=1
R32 32 25 1.2MEG
R34 34 29 1.2MEG
I34 3 34 DC 1U AC 0
I32 3 32 DC 1U AC 0
V64 3 64 DC 1.8302
V60 60 62 DC 1.0897
V62 62 4 DC .8547
M23 25 2 23 3 PCH W=90U L=2U AD=2560P PD=3328U AS=2688P
PS=3494U M=1
M47 43 43 3 3 PCH W=60U L=4U M=1
M43 43 34 27 GNDS NCH W=4U L=4U M=1
M45 45 32 27 GNDS NCH W=4U L=4U M=1
M73 76 51 4 GNDS NCH W=5U L=0.8U M=20
M25 25 27 4 GNDS NCH W=500U L=2U AD=1142P PD=1670U AS=1142P
PS=1670U M=1
M71 76 55 3 3 PCH W=20U L=0.8U M=20
M49 45 43 3 3 PCH W=60U L=4U M=1
RC1 44 76 RPO2 10K
R76 76 5 RPO2 100
CM1 29 44 CP1P2 200P
C45 47 76 CP1P2 22P
RC2 54 4 RPO2 10K
CM2 25 54 CP1P2 200P
.ENDS
* MODELS for LEVEL 3 PSpice
*
.MODEL PCH PMOS (LEVEL=3 TOX=30E-9 CGDO=1.80e-10 CGSO=1.80e-10
CJ=7.199E-4 CJSW=3.40E-10
+AF=1.05 KF=1.0e-31 JS=4.0e-7 JSSW=3.0e-13 RSH=117 MJ=.47 MJSW=.16
VFB=-0.34 PHI=0.71 VTO=-.892
+LD=12E-9 WD=43E-9 TPG=+1 GAMMA=0.6)

.MODEL NCH NMOS (LEVEL=3 TOX=30E-9 CGDO=1.55e-10 CGSO=1.55e-10
CJ=6.300E-4 CJSW=3.83E-10
+AF=1.05 KF=2.6e-31 JS=2.0e-7 JSSW=5e-13 RSH=68 MJ=.25 MJSW=.11 VFB=-
0.784 PHI=0.792 VTO=.81
+LD=34E-9 WD=17E-9 TPG=-1 GAMMA=0.6)

.MODEL RPO2 RES (R=1 TC1=6.3e-4 TC2= 1.1e-6)
.MODEL RNW RES (R=1 TC1=5.5e-3 TC2=-1.3e-5)
.MODEL CP1P2 CAP (C=1)
*.ENDS
*.ENDS OPA336
*