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--- In LTspice@..., "Berns" <microscopeanywhere@> wrote:

Okay I got the help file going on caps and its saying:
Syntax: Cnnn n1 n2 Q=<expression> [ic=<value>] [m=<value>]

I suppose that when I specify an expression for the charge that
says something like: Q=100pF*x then at transient analysis for
some PWL source I should be able to command to LTspice to measure
the capacitance for me?

The best way to measure capacitance as a function of voltage is
in an .ac analysis performed at a single frequency with voltage
stepped as a parameter. The .ac and .step commands might be:

.ac list {.5/pi} ; single frequency .ac analysis
.step dec param x 1 100 10 ; step x logarithmically from 1 to 100
V1 1 0 {x} ac=1 ; ac voltage source with its dc value stepped as x
C1 1 0 Q=1n*x ; here x is the voltage across C1

In the waveform viewer, with trace math, capacitance can be
plotted with the expression:

im(I(C1))*2*Pi*f, where f is the .ac analysis frequency.

By selecting f=1/(2*Pi) in the single frequency .ac analysis
capacitance may simply be directly plotted as im(I(C1)).

EE 101 says for capacitors: Q=CV and Icap=C*dV/dt

For a voltage dependent capacitance, charge must be solved for the
integral of capacitance with respect to voltage:

Q = int C(v)*dv

which will agree with Q = C*V only when C is independent of voltage.

For example, Cgd in LTspice's VDMOS is expressed as a function of
the model parameters Cgdmax, Cgdmin and "a".

Cgd=s*atan(-a*x)+y, where s=(Cgdmax-Cgdmin)/(1+Pi/2) and y=Cgdmax-s

Note that here x is the voltage across Cgd.

To express this as a function of Q (charge) in LTspice's behavioral
capacitor, the integral of this expression must be solved with
respect to the Cgd voltage, x. Fortunately, the Internet has lots
of tables of integrals online, making it easier to find the
solution, which is:

Q=s*(x*atan(-a*x)-ln(1+(-a*x)**2)/(-a*2))+y*x

If this is plugged into the behavioral capacitor,

C1 1 0 Q=s*(x*atan(-a*x)-ln(1+(-a*x)**2)/(-a*2))+y*x

it will have the same voltage dependency a Cgd in LTspice's VDMOS
model (assuming the same values for the parameters Cgdmax, Cgdmin
and a).

Regards -- analogspiceman

--- In LTspice@..., rainbowsally wrote:

THD-prob (probable bug) demo is here

in this file. THD-prob.zip

A netlist node cannot have two names (one will be ignored).
The jumper component is supposed to allow a net to be given
a name for each side of the jumper, but only one will appear
in the final netlist. If you insist on two names, you should
separate the nodes with a zero value voltage source. If you
only need one name at a time, then simply move the currently
unneeded name off the net and swap later when needed. -- a.s.




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Hi ppl,

I thought I would search for it - to test my abilities - I didn't find it.
I am learning a fair amount by just reading this group and others
troubles. So as my first reply to the group I will advice what I found on
a circuit site<>.
HIH - sorry if i am wrong - sounds like the guy knew what he was talking
about.

An optocoupler is just a current-controlled current source, pretty much,
close enough. That already exists. Maybe put a small capacitor across it to
simulate slowness.

(2nd post attempt - just to test it gets posted more then anything )
Thanks,
Colin




--
Thanks,
Colin



[Non-text portions of this message have been removed]

The LP339 device is an open collector output and expects a resistor pull up to the positive rail.

--- In LTspice@..., rainbowsally<rainbowsally@...> wrote:

This file:
RS/my-circuits/lp339_lp2901.asc
found here


Is a schematic from TI but the default transistors (copied from the
examples/Educational/NE555.asc file couldn't pull the output up so I cut
and jumpered one transistor to Vcc.

I messed with the few parameters to attempt to model a smaller
transistor geometry but that didn't work.

Anyway, the schematic is accurate and interesting, but there may be one
error in it and if anyone can correct that without monkeying with the
current sources, it would be much appreciated.

Thanks.

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