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--- In LTspice@..., "Helmut Sennewald
<helmutsennewald@y...>" <helmutsennewald@y...> wrote:

--- In LTspice@..., "bunnyblues2001
<bunnyblues2001@y...>" <bunnyblues2001@y...> wrote:

I need a model for a gas discharge tube similar to the Siemens A81-
C90X, if anyone can help I'd appreciate it. I have just started to
use LTSpice and would like to know if there is any information out
there that shows how to convert a manufactures model to something
that will keep LTSpice happy. I was hoping to use the DIAC that

comes

with LTSpice but found out I have to supply my own model. Any hints
for a day-old user how to do this? So far it's a cool program.

Hello,
are you referencing this model?

It contains lines with non LTSpice syntax.
These lines have to be modified.

Do you have a datasheet or any SPICE parameter?

Best Regards
Helmut

Thanks for the quick response. I have a few datasheets for different
devices. I don't now what parameters I'll need but not knowing has
never stopped me from giving it a shot.

--- In LTspice@..., "bunnyblues2001
<bunnyblues2001@y...>" <bunnyblues2001@y...> wrote:

I need a model for a gas discharge tube similar to the Siemens A81-
C90X, if anyone can help I'd appreciate it. I have just started to
use LTSpice and would like to know if there is any information out
there that shows how to convert a manufactures model to something
that will keep LTSpice happy. I was hoping to use the DIAC that

comes

with LTSpice but found out I have to supply my own model. Any hints
for a day-old user how to do this? So far it's a cool program.

Hello,
are you referencing this model?

It contains lines with non LTSpice syntax.
These lines have to be modified.

Do you have a datasheet or any SPICE parameter?

Best Regards
Helmut

I need a model for a gas discharge tube similar to the Siemens A81-
C90X, if anyone can help I'd appreciate it. I have just started to
use LTSpice and would like to know if there is any information out
there that shows how to convert a manufactures model to something
that will keep LTSpice happy. I was hoping to use the DIAC that comes
with LTSpice but found out I have to supply my own model. Any hints
for a day-old user how to do this? So far it's a cool program.

Many thanks for your help. I moved the Spice
directive ".lib opamp.sub" to the top level as
suggested, and the sim ran. It seems rather
awkward to have to remember to put all
hierarchical subcircuit calls at the top
level when constructing a hierarchical
schematic, but I guess there's no way around
it. (Is there?)

a few minutes ago I sent Mike Engelhardt this
question and asked him to answer into this
thread at the YAHOO-LTSpice group.

Oh, yes. That is awkward. I'll see if I can't
improve on this.

I put up a version today(2.00t) that enables nested
subcircuit definitions. Initial tests suggest the
parameter passing is properly scoped. Please report
any problems or crashes as soon as you detect them.

--Mike

__________________________________________________
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--- In LTspice@..., "gm4dij <brian.howie@b...>"
<brian.howie@b...> wrote:

--- In LTspice@..., Panama Mike <panamatex@y...> wrote:

You might be able to use the rand() function
to get what you're looking for. Check the
example ./LTC/SwCADIII/examples/Educational/PLL.asc
There it is used to generate a random bit stream
by boolean comparison to 0.5.

--Mike
--- "ingodettmann
<ingod@y...>"
<ingod@y...> wrote:

Hi everbody,

does anyone know, how I can add a noise source in a
transient
simulation (if it is possible at all)?
I tried to modell a noise source with a behavioral
voltage source
but i didn't work.

rand and white on their own are no use -these are rectangular

random

variables.

Use a behavioural voltage source with V for example

V=SQRT(-2*LN(white(time*1.07G)+0.5))*COS(2*PI*(white
((time*0.93G+0.5)))


This is the Box-Mueller algorithm for Gaussian Noise. You need two
independent random variables. The factors 1.07 and 0.93 is an

attempt

to do this. You will need to alter these, and the time step to get
what you want. You also may need to scale to get the correct rms
value in your noise bandwidth.

It's not perfect.

Hello Brian,
thanks for the formula. I googled and found this reference.


I couldn't resist to test it immediately in LTSPICE.
I have got some extremely high peaks(30V) at 47us, 48us and 84us
with the setting ".tran 0 100000n 0 0.5n".
So the formula needs a little change to avoid extreme values at
log(0).


The original formula:

V=SQRT(-2*LN(white(time*1.07G)+0.5))*COS(2*PI*(white(time*0.93G+0.5)))

My slightly modified formula for LTSpice:

V=SQRT(-2*LN(0.999997*white(time*1.07e9) +0.50001))*COS(2*PI*white
(time*0.93e9+0.5))

This B-source doesn't have the above mentioned "defects".

Best Regards
Helmut

--- In LTspice@..., Panama Mike <panamatex@y...> wrote:

You might be able to use the rand() function
to get what you're looking for. Check the
example ./LTC/SwCADIII/examples/Educational/PLL.asc
There it is used to generate a random bit stream
by boolean comparison to 0.5.

--Mike
--- "ingodettmann
<ingod@y...>"
<ingod@y...> wrote:

Hi everbody,

does anyone know, how I can add a noise source in a
transient
simulation (if it is possible at all)?
I tried to modell a noise source with a behavioral
voltage source
but i didn't work.

rand and white on their own are no use -these are rectangular random
variables.

Use a behavioural voltage source with V for example

V=SQRT(-2*LN(white(time*1.07G)+0.5))*COS(2*PI*(white
((time*0.93G+0.5)))


This is the Box-Mueller algorithm for Gaussian Noise. You need two
independent random variables. The factors 1.07 and 0.93 is an attempt
to do this. You will need to alter these, and the time step to get
what you want. You also may need to scale to get the correct rms
value in your noise bandwidth.

It's not perfect.

Brian Howie

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Many thanks for your help. I moved the Spice
directive ".lib opamp.sub" to the top level as
suggested, and the sim ran. It seems rather
awkward to have to remember to put all
hierarchical subcircuit calls at the top
level when constructing a hierarchical
schematic, but I guess there's no way around
it. (Is there?)

a few minutes ago I sent Mike Engelhardt this
question and asked him to answer into this
thread at the YAHOO-LTSpice group.

Oh, yes. That is awkward. I'll see if I can't
improve on this. The situation comes about
historically because while the academic codes
often do allow nested subcircuit definitions,
the commercial codes do not. However, the
commercial codes allow subcircuit parameters to
be passed, which is usually more useful.
Anyway, LTspice follows the commercial
standards. Maybe I can make it follow a
superset language.

--Mike

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Helmut and Mike,

Many thanks for your help. I moved the Spice directive ".lib
opamp.sub" to the top level as suggested, and the sim ran. It

seems

rather awkward to have to remember to put all hierarchical
subcircuit calls at the top level when constructing a hierarchical
schematic, but I guess there's no way around it. (Is there?)

Hello Ron,
a few minutes ago I sent Mike Engelhardt this question and asked him
to answer into this thread at the YAHOO-LTSpice group.

Best Regards
Helmut

--- In LTspice@..., "Helmut Sennewald
<helmutsennewald@y...>" <helmutsennewald@y...> wrote:

--- In LTspice@..., Panama Mike <panamatex@y...> wrote:

The error message occurs when the schematic
resloves to netlist something like this:

.subckt N1 N2 N3 name1
.subckt N4 N5 N6 name2
[...]
.ends name2
.ends name1

The definition of name2 is inside name1.
Perhaps you have a subcircuit *defined*
in the circuit you want to include a subcircuit.
You can't nest definitions, but there's no
limit on the the depth of the hierarchy.

Hello Mike,

thanks for the tip with the nested subcircuit.
I had the chance to get the circuit files from Ron and remembering
your advice, I immediatly looked into the LTSpice netlist.
It was exactly the problem as you have expected.


Let me sketch the three level hierarchy:

Top: Level-1 schematic: ressitors, instance of level-2

Next Level-2: instance of level-3, resistors, opamp.asy
.include opamp.sub

Next Level-3: transistors, diodes, G-sources


The problem was the ".include opamp.sub" statement in Level-2.
After I moved this statement to the top level-1, the simulation

was

possible.


Top: Level-1 schematic: ressitors, instance of level-2
.include opamp.sub

Next Level-2: instance of level-3, resistors, opamp.asy

Next Level-3: transistors, diodes, G-sources



Partial netlist before change:
...
.subckt rc4200_sq cos sin Vref Vee out
...
.PARAM Ro={4*ampl*ampl*K/160e-6}
.PARAM K=1
.lib opamp.sub
.ends rc4200_sq

...
.backanno
.end


Partial netlist after change:
...
.subckt rc4200_sq cos sin Vref Vee out
...
.PARAM Ro={4*ampl*ampl*K/160e-6}
.PARAM K=1
.ends rc4200_sq

....
.inc opamp.sub
.backanno
.end


Hello Ron,
your opamp device is already under "lib&#92;asy&#92;opamps" in the LTSpice
path and the opamp.sub is directly under "lib&#92;sub". So you don't
need it additionally in your working directory.

Best Regards
Helmut

Helmut and Mike,

Many thanks for your help. I moved the Spice directive ".lib
opamp.sub" to the top level as suggested, and the sim ran. It seems
rather awkward to have to remember to put all hierarchical
subcircuit calls at the top level when constructing a hierarchical
schematic, but I guess there's no way around it. (Is there?)

Thanks again,

Ron

--- "rmaxh <rmaxh@y...>" <rmaxh@y...> wrote:

I created a symbol to represent a schematic (symbol
saved as "block"
(.asy)). When I placed it in a higher level
schematic and tried to
run a sim, I got an error message telling me that
subcircuits cannot
be nested. The lower level schematic does have a
subcircuit in it,
and a .lib directive to call that subcircuit, but
this must not be a
limitation of heirarchical schematics, as it would
severely limit
its usefulness. I'm certain I'm doing something
wrong. Anyone know
what that might be?

Ron Harrison

__________________________________________________
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--- In LTspice@..., Panama Mike <panamatex@y...> wrote:

The error message occurs when the schematic
resloves to netlist something like this:

.subckt N1 N2 N3 name1
.subckt N4 N5 N6 name2
[...]
.ends name2
.ends name1

The definition of name2 is inside name1.
Perhaps you have a subcircuit *defined*
in the circuit you want to include a subcircuit.
You can't nest definitions, but there's no
limit on the the depth of the hierarchy.

Hello Mike,

thanks for the tip with the nested subcircuit.
I had the chance to get the circuit files from Ron and remembering
your advice, I immediatly looked into the LTSpice netlist.
It was exactly the problem as you have expected.


Let me sketch the three level hierarchy:

Top: Level-1 schematic: ressitors, instance of level-2

Next Level-2: instance of level-3, resistors, opamp.asy
.include opamp.sub

Next Level-3: transistors, diodes, G-sources


The problem was the ".include opamp.sub" statement in Level-2.
After I moved this statement to the top level-1, the simulation was
possible.


Top: Level-1 schematic: ressitors, instance of level-2
.include opamp.sub

Next Level-2: instance of level-3, resistors, opamp.asy

Next Level-3: transistors, diodes, G-sources



Partial netlist before change:
...
.subckt rc4200_sq cos sin Vref Vee out
...
.PARAM Ro={4*ampl*ampl*K/160e-6}
.PARAM K=1
.lib opamp.sub
.ends rc4200_sq

...
.backanno
.end


Partial netlist after change:
...
.subckt rc4200_sq cos sin Vref Vee out
...
.PARAM Ro={4*ampl*ampl*K/160e-6}
.PARAM K=1
.ends rc4200_sq

....
.inc opamp.sub
.backanno
.end


Hello Ron,
your opamp device is already under "lib&#92;asy&#92;opamps" in the LTSpice
path and the opamp.sub is directly under "lib&#92;sub". So you don't
need it additionally in your working directory.

Best Regards
Helmut

--- "rmaxh <rmaxh@y...>" <rmaxh@y...> wrote:

I created a symbol to represent a schematic (symbol
saved as "block"
(.asy)). When I placed it in a higher level
schematic and tried to
run a sim, I got an error message telling me that
subcircuits cannot
be nested. The lower level schematic does have a
subcircuit in it,
and a .lib directive to call that subcircuit, but
this must not be a
limitation of heirarchical schematics, as it would
severely limit
its usefulness. I'm certain I'm doing something
wrong. Anyone know
what that might be?

Ron Harrison

__________________________________________________
Do you Yahoo!?
Yahoo! Mail Plus - Powerful. Affordable. Sign up now.

The error message occurs when the schematic
resloves to netlist something like this:

.subckt N1 N2 N3 name1
.subckt N4 N5 N6 name2
[...]
.ends name2
.ends name1

The definition of name2 is inside name1.
Perhaps you have a subcircuit *defined*
in the circuit you want to include a subcircuit.
You can't nest definitions, but there's no
limit on the the depth of the hierarchy.

--Mike

--- "rmaxh <rmaxh@...>" <rmaxh@...> wrote:

I created a symbol to represent a schematic (symbol
saved as "block"
(.asy)). When I placed it in a higher level
schematic and tried to
run a sim, I got an error message telling me that
subcircuits cannot
be nested. The lower level schematic does have a
subcircuit in it,
and a .lib directive to call that subcircuit, but
this must not be a
limitation of heirarchical schematics, as it would
severely limit
its usefulness. I'm certain I'm doing something
wrong. Anyone know
what that might be?

Ron Harrison

__________________________________________________
Do you Yahoo!?
Yahoo! Mail Plus - Powerful. Affordable. Sign up now.

I created a symbol to represent a schematic (symbol saved as "block"
(.asy)). When I placed it in a higher level schematic and tried to
run a sim, I got an error message telling me that subcircuits cannot
be nested. The lower level schematic does have a subcircuit in it,
and a .lib directive to call that subcircuit, but this must not be a
limitation of heirarchical schematics, as it would severely limit
its usefulness. I'm certain I'm doing something wrong. Anyone know
what that might be?

Ron Harrison

--- In LTspice@..., "polapart <sahawley@m...>"
<sahawley@m...> wrote:

Is there a simple way to convert TI models to run in LTSpice?

Hello,
there are two chances for your opamp models.
The first one is creating a symbol for every opamp type you want to
use. I think this is described in the LTSpice help pages.
The other chance is to make one general symbol. Then you have to
change only the value of the symbol in the schematic.
See my older posting in this group:
Re: Converting PSpice MOSFET models


I recommend to upgrade to the latest LTSpice, version 2.00k at this
writing. It's easier to make symbols/models with the new 2.x release.

Best Regards
Helmut

Dear Mr. Sennewald,

Thank you very much! You gave the final hint to solve the problem! And I already believed in a bug...
As you said, there is no semiconductor device in my circuit. In fact, what you had was the whole circuit... only one line was missing: the line which indicates what library I use. After deleting it, my circuit worked!
I guess, my capacity Cubk (which should mean "C unbekannt" (= "C unknown") ) had the same name as any of my models in a library. I will look for it.

Thank you very much for your help!

Truly Yours

Bernhard

______________________________________________________________________________
ASCII-Bilder und SMS-Sprueche bei WEB.DE FreeMail - auswaehlen, einfuegen
und versenden!

--- In LTspice@..., "ingodettmann <ingod@y...>"
<ingod@y...> wrote:

Hi everbody,

does anyone know, how I can add a noise source in a transient
simulation (if it is possible at all)?
I tried to modell a noise source with a behavioral voltage source
but i didn't work.

Hello Ingo,

there is a very easy way to make such a noise source.
Firstly we should be aware that the rand() funktion has equal
probability for every voltage level between 0 and 1.
This is not like a gaussian noise where you have higher values with
lower probabilty. I remembered a theorem that the generated noise
becomes more gaussian by adding many such noise sources.
I have preferred three sources.

Example:
Digital noise clock is 1e4Hz. "time" is the keyword for time in
the .tran analysis. You can use it in your B-sources.
You have to increase the rand() frequency 1e4 to your requirements.
I think that the offset parameter in the rand() function should be
increased proportionally to the frequency. The intention of this
offset parameter is to make the three rand() functions more like
independant noise sources.

Best Regards
Helmut


Example; f=1.0e4

B1: V=2*rand(time*1e4)
B2: V=2*rand(time*1e4+0.0911e4)
B3: V=2*rand(time*1e4+0.2131e4)

.tran 0 100m 0 10u


Example; f=1.0e9

B1: V=2*rand(time*10e9)
B2: V=2*rand(time*10e9+0.0911e9)
B3: V=2*rand(time*10e9+0.2131e9)

.tran 0 1u 0 0.1n


netlist
-------

*
B1 N001 0 V=2*rand(time*1e9+0.2131e9)
B2 N002 N001 V=2*rand(time*1e9+0.0911e9)
B3 N003 N002 V=2*rand(time*1e9)
R1 N003 out 50
C1 out 0 1p
.tran 0 1u 0 0.1n
.backanno
.end


Schematic
---------

SHEET 1 912 712
WIRE 192 80 192 32
WIRE 192 208 192 160
WIRE 192 -96 192 -48
WIRE 192 -176 192 -224
WIRE 192 -224 464 -224
WIRE 544 -224 576 -224
WIRE 576 -224 576 -192
WIRE 576 -128 576 -96
FLAG 192 208 GND
FLAG 576 -96 0
FLAG 576 -224 out
SYMBOL BV 192 64 R0
SYMATTR InstName B1
SYMATTR Value V=2*rand(time*1e9+0.2131e9)
SYMBOL bv 192 -64 R0
SYMATTR InstName B2
SYMATTR Value V=2*rand(time*1e9+0.0911e9)
SYMBOL bv 192 -192 R0
SYMATTR InstName B3
SYMATTR Value V=2*rand(time*1e9)
SYMBOL res 448 -208 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL cap 560 -192 R0
SYMATTR InstName C1
SYMATTR Value 1p
TEXT 192 -256 Left 0 !.tran 0 1u 0 0.1n

--- In LTspice@..., <Bernhard_Kraemer@w...> wrote:

Hello,

After a re-install of my system, I downloaded the newest edition of
LTSpice. Now I tried out to simulate a simple circuit, and I

discovered that whatever it is, my circuit works well, but with the >
STEP command I get the error :

Multiple instances of "Cjo=1.0760e-12".

Hello Bernhard,

Cjo is normally a parameter of a semiconductor device. It seems
you have any such device in your circuit, but your posted netlist
doesn't show it.

What could this possibly be? What could I do to solve the problem?
Here my short circuit:

Kondensatorme?bruecke

*Widerst?nde

R1 2 0 1K
R2 3 0 {var}

*Kondensatoren

C1 1 2 1u
Cubk 1 3 2u

*Strom- und Spannungsquellen

Vsin 1 0 SIN(0 5 200)

.PARAM var=1K

** Analysis setup **
.OP
.STEP LIN PARAM var 1 10K 1K <<<< This Line gives the error!
.tran 50us 50m

.END

I have tried your circuit with with LTSpice version 2.00k
and it has been simulated without any error. Firstly I used the
schematic editor to enter the circuit. Then I tried your text version
also sucessfully.
When I look to my netlists they are eactly the same like yours.

Which version of LTSpice are you using?
Please try the latest 2.00k.
If you really use already 2.00k, then feel free to send me your
original .asc file and/or your netlist file for further investigation.


Best Regards
Helmut

HelmutSennewald@...



Textversion:
-------------

*Kondensatorme?bruecke
*Widerst?nde

R1 2 0 1K
R2 3 0 {var}

*Kondensatoren

C1 1 2 1u
Cubk 1 3 2u

*Strom- und Spannungsquellen

Vsin 1 0 SIN(0 5 200)

.PARAM var=1K

** Analysis setup **
.OP
.STEP LIN PARAM var 1 10K 1K
.tran 50u 50m

.END


From schematic version:
-----------------------

*
R1 2 0 1k
R2 3 0 {var}
Cubk 1 3 2?
C1 1 2 1?
Vsin 1 0 SINE(0 5 200)
.PARAM var=1K
.STEP LIN PARAM var 1 10K 1K
.tran 50us 50m
.backanno
.end

Hello,

After a re-install of my system, I downloaded the newest edition of LTSpice. Now I tried out to simulate a simple circuit, and I discovered that whatever it is, my circuit works well, but with the STEP command I get the error :

Multiple instances of "Cjo=1.0760e-12".

What could this possibly be? What could I do to solve the problem?
Here my short circuit:

Kondensatorme?bruecke

*Widerst?nde

R1 2 0 1K
R2 3 0 {var}

*Kondensatoren

C1 1 2 1u
Cubk 1 3 2u

*Strom- und Spannungsquellen

Vsin 1 0 SIN(0 5 200)

.PARAM var=1K

** Analysis setup **
.OP
.STEP LIN PARAM var 1 10K 1K <<<< This Line gives the error!
.tran 50us 50m

.END



Greetings,

Bernhard Kr?mer
______________________________________________________________________________
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You can run them if they're defined with, e.g.,
PSpice subcircuits. Latter versions of LTspice
comes with documenation about making symbols
for 3rd party devices.

--Mike

--- "polapart <sahawley@...>" <sahawley@...>
wrote:

Is there a simple way to convert TI models to run in
LTSpice?

__________________________________________________
Do you Yahoo!?
Yahoo! Mail Plus - Powerful. Affordable. Sign up now.

You might be able to use the rand() function
to get what you're looking for. Check the
example ./LTC/SwCADIII/examples/Educational/PLL.asc
There it is used to generate a random bit stream
by boolean comparison to 0.5.

--Mike
--- "ingodettmann
<ingod@...>"
<ingod@...> wrote:

Hi everbody,

does anyone know, how I can add a noise source in a
transient
simulation (if it is possible at all)?
I tried to modell a noise source with a behavioral
voltage source
but i didn't work.

Thanks,

Ingo

__________________________________________________
Do you Yahoo!?
Yahoo! Mail Plus - Powerful. Affordable. Sign up now.

Is there a simple way to convert TI models to run in LTSpice?