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--- In LTspice@..., "Helmut Sennewald >

The attached sample circuit helps to understand the syntax.
This file is also from Mike.

Hello Mike,
are there even more parameters for digital parts?

Best Regards
Helmut

Thank you very much Helmut,

In the meantime, I debugged my digital design (a simple FSM) on
another mixed-mode simulator (evaluation version of Microcap). Now
I'll try to implement it with LTSpice where my main analog design is,
using Mikes's example.
Probably more feedback at the end of the week-end.

Best regards

Christian

--- In LTspice@..., "neel_christian <neel_c@c...>"
<neel_c@c...> wrote:

Hello Group,

I discovered LTSpice a few days ago and I find it very usefull,

fun

and easy-to-use :-)

I am now trying to use mixed-mode simulation, and I cannot edit nor
see the models of simple parts like DFLOP (I just want to modify

Hold

Time, Threshold, etc.). I did it easily for simple analog parts

(like

nmos,pmos), but no way to find a file (even after a search in the
help files and FAQ) for digital parts...maybe I should buy new
glasses.

A Hint?

Hello Christian,
new glasses wouldn't help. I had the same question half a year ago.
The developer of LTSpice, Mike Engelhardt, kindky send me the
necessary information.
By the way, he is around here in the group as Panama Mike,
but keep it for yourself. It is a secret.

The attached sample circuit helps to understand the syntax.
This file is also from Mike.

Hello Mike,
are there even more parameters for digital parts?

Best Regards
Helmut


Original answer from Mike:
--------------------------
The low and high levels are given with Vlow and Vhigh. The
logic thresholds default to half way between but can be
specified with ref. Hysteresis is not possible for gates,
but only for the Schmitt devices. Attached is and example
that hopefully illustrates. Tripdt is a type of temporal
accuracy it should strive for in switching.

Sample circuit file "gate.asc":
-------------------------------

Version 3
SHEET 1 892 692
WIRE 408 304 408 320
WIRE 420 292 436 292
WIRE 420 300 520 300
WIRE 344 356 344 340
WIRE 344 320 344 296
WIRE 344 296 404 296
WIRE 520 300 520 308
WIRE 520 328 520 340
WIRE 408 244 408 260
WIRE 420 232 436 232
WIRE 404 236 344 236
WIRE 344 236 344 296
WIRE 344 236 344 200
WIRE 344 200 404 200
WIRE 420 200 452 200
WIRE 404 204 404 212
FLAG 408 320 GND
FLAG 344 356 GND
FLAG 520 340 GND
FLAG 408 260 GND
FLAG 404 212 GND
SYMBOL digital&#92;and 412 280 R0
WINDOW 0 4 6 Left 0
WINDOW 3 4 28 Left 0
WINDOW 39 4 44 Left 0
WINDOW 40 4 52 Left 0
WINDOW 123 4 36 Left 0
SYMATTR InstName A1
SYMATTR Value Vhigh=5
SYMATTR Value2 Vlow=0 Rout=100
SYMATTR SpiceModel AND
SYMATTR SpiceLine Ref=2 Td=50n tripdt=3n
SYMATTR SpiceLine2 Trise=20n Tfall=40n
SYMBOL voltage 344 316 R0
WINDOW 0 6 4 Left 0
WINDOW 3 6 26 Left 0
SYMATTR InstName V1
SYMATTR Value pulse(0 5 0 100n 100n 0 200n)
SYMBOL res 516 304 R0
WINDOW 0 9 10 Left 0
WINDOW 3 9 19 Left 0
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL digital&#92;and 412 220 R0
WINDOW 0 4 6 Left 0
WINDOW 3 4 28 Left 0
WINDOW 39 4 44 Left 0
WINDOW 40 4 52 Left 0
WINDOW 123 4 36 Left 0
SYMATTR InstName A2
SYMATTR Value Vhigh=5
SYMATTR Value2 Vlow=0 Rout=100
SYMATTR SpiceModel AND
SYMATTR SpiceLine Ref=2 Td=50n tripdt=3n
SYMATTR SpiceLine2 Tau=10n
SYMBOL digital&#92;schmtbuf 404 184 R0
WINDOW 0 2 8 Left 0
WINDOW 3 5 24 Left 0
WINDOW 123 5 32 Left 0
SYMATTR InstName A3
SYMATTR Value Vt=2.5 Vh=1
SYMATTR Value2 tripdt=3n
SYMATTR SpiceModel SCHMITT
text 328 368 Left 0 !.tran 1u

Hello Group,

I discovered LTSpice a few days ago and I find it very usefull, fun
and easy-to-use :-)

I am now trying to use mixed-mode simulation, and I cannot edit nor
see the models of simple parts like DFLOP (I just want to modify Hold
Time, Threshold, etc.). I did it easily for simple analog parts (like
nmos,pmos), but no way to find a file (even after a search in the
help files and FAQ) for digital parts...maybe I should buy new
glasses.

A Hint?

Thank you in advance for your help

Christian Néel

Looking into the model list I am not able to find

the

models for a semiconductor (diffused) resistors and
capacitors. They are not very important but some
netlists are using them. Are these models available
in LTSpice? They are standard models in Berkeley
Spice3, may be useful to add them for compatibility.

You can use the standard resistor and capacitors model
statements. It should be able to understand both
Berkeley and PSpice syntax.

Is there an upper limit for the number of components
in the standard.* libraries

(diode,resistor,capacitor...)?

Absolutely not, but there isn't any facility there you
help you organize your models. If you wish, you can
also keep your own libraries separate and include them
by putting a SPICE directive on the schematic of the
form ".lib <filenamepath>"

Using the .STEP statement it seems difficult to
analyze the different waveforms because it is not
possible (is it right?) to understand which value of
the parameter is related with a particular waveform.
Is there a way to show which value is used with any
waveforms?

Yes, it can be difficult. You can navigate an
attached
cursor from one dataset to the next with the up/down
keyboard cursor keys.

--Mike

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Hi everybody,

I am a new user of LTSpice.

Looking into the model list I am not
able to find the models for a semiconducor (diffused) resistors and capacitors.
They are not very important but some netlists are using them.
Are these models available in LTSpice? They are standard models in Berkeley Spice3, may be useful to add them for compatibility.


Is there an upper limit for the numeber of components in the standard.*
libraries (diode,resistor,capacitor...)?

Using the .STEP statement it seems difficult to analyze the different waveforms because it is not possible (is it right?) to understand which
value of the parameter is related with a particular waveform. Is there a
way to show which value is used with any waveforms?


Regards

Massimo


--

''~``
( o o )
+------------------.oooO--(_)--Oooo.------------------+
| |
| e-mail: gaspari@... |
| |
| ICQ # = 166939207 |
| |
| PGP fingerprint16: |
| 76 80 F2 F9 8D 70 F3 D1 42 2B CD 80 29 49 CB 25 |
| |
| .oooO |
| ( ) Oooo. |
+---------------------&#92; (----( )--------------------+
&#92;_) ) /
(_/

I need a model for a gas discharge tube similar to the Siemens A81-
C90X, if anyone can help I'd appreciate it. I have just started to
use LTSpice and would like to know if there is any information out
there that shows how to convert a manufactures model to something
that will keep LTSpice happy. I was hoping to use the DIAC that comes
with LTSpice but found out I have to supply my own model. Any hints
for a day-old user how to do this? So far it's a cool program.


To unsubscribe from this group, send an email to:
LTspice-unsubscribe@...



Your use of Yahoo! Groups is subject to

Try

Their may be something there you can use.

Regards

Brian

--
Brian Howie | Tel: 0131 343 5590
BAE SYSTEMS | Fax: 0131 343 5050
Sensor Systems Division | Email brian.howie@...
Silverknowes | bhowie@...
Edinburgh EH4 4AD | Web site www.baesystems.com

--- In LTspice@..., "Helmut Sennewald
<helmutsennewald@y...>" <helmutsennewald@y...> wrote:

--- In LTspice@..., "bunnyblues2001
<bunnyblues2001@y...>" <bunnyblues2001@y...> wrote:

I need a model for a gas discharge tube similar to the Siemens A81-
C90X, if anyone can help I'd appreciate it. I have just started to
use LTSpice and would like to know if there is any information out
there that shows how to convert a manufactures model to something
that will keep LTSpice happy. I was hoping to use the DIAC that

comes

with LTSpice but found out I have to supply my own model. Any hints
for a day-old user how to do this? So far it's a cool program.

Hello,
are you referencing this model?

It contains lines with non LTSpice syntax.
These lines have to be modified.

Do you have a datasheet or any SPICE parameter?

Best Regards
Helmut

Thanks for the quick response. I have a few datasheets for different
devices. I don't now what parameters I'll need but not knowing has
never stopped me from giving it a shot.

--- In LTspice@..., "bunnyblues2001
<bunnyblues2001@y...>" <bunnyblues2001@y...> wrote:

I need a model for a gas discharge tube similar to the Siemens A81-
C90X, if anyone can help I'd appreciate it. I have just started to
use LTSpice and would like to know if there is any information out
there that shows how to convert a manufactures model to something
that will keep LTSpice happy. I was hoping to use the DIAC that

comes

with LTSpice but found out I have to supply my own model. Any hints
for a day-old user how to do this? So far it's a cool program.

Hello,
are you referencing this model?

It contains lines with non LTSpice syntax.
These lines have to be modified.

Do you have a datasheet or any SPICE parameter?

Best Regards
Helmut

I need a model for a gas discharge tube similar to the Siemens A81-
C90X, if anyone can help I'd appreciate it. I have just started to
use LTSpice and would like to know if there is any information out
there that shows how to convert a manufactures model to something
that will keep LTSpice happy. I was hoping to use the DIAC that comes
with LTSpice but found out I have to supply my own model. Any hints
for a day-old user how to do this? So far it's a cool program.

Many thanks for your help. I moved the Spice
directive ".lib opamp.sub" to the top level as
suggested, and the sim ran. It seems rather
awkward to have to remember to put all
hierarchical subcircuit calls at the top
level when constructing a hierarchical
schematic, but I guess there's no way around
it. (Is there?)

a few minutes ago I sent Mike Engelhardt this
question and asked him to answer into this
thread at the YAHOO-LTSpice group.

Oh, yes. That is awkward. I'll see if I can't
improve on this.

I put up a version today(2.00t) that enables nested
subcircuit definitions. Initial tests suggest the
parameter passing is properly scoped. Please report
any problems or crashes as soon as you detect them.

--Mike

__________________________________________________
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--- In LTspice@..., "gm4dij <brian.howie@b...>"
<brian.howie@b...> wrote:

--- In LTspice@..., Panama Mike <panamatex@y...> wrote:

You might be able to use the rand() function
to get what you're looking for. Check the
example ./LTC/SwCADIII/examples/Educational/PLL.asc
There it is used to generate a random bit stream
by boolean comparison to 0.5.

--Mike
--- "ingodettmann
<ingod@y...>"
<ingod@y...> wrote:

Hi everbody,

does anyone know, how I can add a noise source in a
transient
simulation (if it is possible at all)?
I tried to modell a noise source with a behavioral
voltage source
but i didn't work.

rand and white on their own are no use -these are rectangular

random

variables.

Use a behavioural voltage source with V for example

V=SQRT(-2*LN(white(time*1.07G)+0.5))*COS(2*PI*(white
((time*0.93G+0.5)))


This is the Box-Mueller algorithm for Gaussian Noise. You need two
independent random variables. The factors 1.07 and 0.93 is an

attempt

to do this. You will need to alter these, and the time step to get
what you want. You also may need to scale to get the correct rms
value in your noise bandwidth.

It's not perfect.

Hello Brian,
thanks for the formula. I googled and found this reference.


I couldn't resist to test it immediately in LTSPICE.
I have got some extremely high peaks(30V) at 47us, 48us and 84us
with the setting ".tran 0 100000n 0 0.5n".
So the formula needs a little change to avoid extreme values at
log(0).


The original formula:

V=SQRT(-2*LN(white(time*1.07G)+0.5))*COS(2*PI*(white(time*0.93G+0.5)))

My slightly modified formula for LTSpice:

V=SQRT(-2*LN(0.999997*white(time*1.07e9) +0.50001))*COS(2*PI*white
(time*0.93e9+0.5))

This B-source doesn't have the above mentioned "defects".

Best Regards
Helmut

--- In LTspice@..., Panama Mike <panamatex@y...> wrote:

You might be able to use the rand() function
to get what you're looking for. Check the
example ./LTC/SwCADIII/examples/Educational/PLL.asc
There it is used to generate a random bit stream
by boolean comparison to 0.5.

--Mike
--- "ingodettmann
<ingod@y...>"
<ingod@y...> wrote:

Hi everbody,

does anyone know, how I can add a noise source in a
transient
simulation (if it is possible at all)?
I tried to modell a noise source with a behavioral
voltage source
but i didn't work.

rand and white on their own are no use -these are rectangular random
variables.

Use a behavioural voltage source with V for example

V=SQRT(-2*LN(white(time*1.07G)+0.5))*COS(2*PI*(white
((time*0.93G+0.5)))


This is the Box-Mueller algorithm for Gaussian Noise. You need two
independent random variables. The factors 1.07 and 0.93 is an attempt
to do this. You will need to alter these, and the time step to get
what you want. You also may need to scale to get the correct rms
value in your noise bandwidth.

It's not perfect.

Brian Howie

Do you Yahoo!?
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Many thanks for your help. I moved the Spice
directive ".lib opamp.sub" to the top level as
suggested, and the sim ran. It seems rather
awkward to have to remember to put all
hierarchical subcircuit calls at the top
level when constructing a hierarchical
schematic, but I guess there's no way around
it. (Is there?)

a few minutes ago I sent Mike Engelhardt this
question and asked him to answer into this
thread at the YAHOO-LTSpice group.

Oh, yes. That is awkward. I'll see if I can't
improve on this. The situation comes about
historically because while the academic codes
often do allow nested subcircuit definitions,
the commercial codes do not. However, the
commercial codes allow subcircuit parameters to
be passed, which is usually more useful.
Anyway, LTspice follows the commercial
standards. Maybe I can make it follow a
superset language.

--Mike

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Helmut and Mike,

Many thanks for your help. I moved the Spice directive ".lib
opamp.sub" to the top level as suggested, and the sim ran. It

seems

rather awkward to have to remember to put all hierarchical
subcircuit calls at the top level when constructing a hierarchical
schematic, but I guess there's no way around it. (Is there?)

Hello Ron,
a few minutes ago I sent Mike Engelhardt this question and asked him
to answer into this thread at the YAHOO-LTSpice group.

Best Regards
Helmut

--- In LTspice@..., "Helmut Sennewald
<helmutsennewald@y...>" <helmutsennewald@y...> wrote:

--- In LTspice@..., Panama Mike <panamatex@y...> wrote:

The error message occurs when the schematic
resloves to netlist something like this:

.subckt N1 N2 N3 name1
.subckt N4 N5 N6 name2
[...]
.ends name2
.ends name1

The definition of name2 is inside name1.
Perhaps you have a subcircuit *defined*
in the circuit you want to include a subcircuit.
You can't nest definitions, but there's no
limit on the the depth of the hierarchy.

Hello Mike,

thanks for the tip with the nested subcircuit.
I had the chance to get the circuit files from Ron and remembering
your advice, I immediatly looked into the LTSpice netlist.
It was exactly the problem as you have expected.


Let me sketch the three level hierarchy:

Top: Level-1 schematic: ressitors, instance of level-2

Next Level-2: instance of level-3, resistors, opamp.asy
.include opamp.sub

Next Level-3: transistors, diodes, G-sources


The problem was the ".include opamp.sub" statement in Level-2.
After I moved this statement to the top level-1, the simulation

was

possible.


Top: Level-1 schematic: ressitors, instance of level-2
.include opamp.sub

Next Level-2: instance of level-3, resistors, opamp.asy

Next Level-3: transistors, diodes, G-sources



Partial netlist before change:
...
.subckt rc4200_sq cos sin Vref Vee out
...
.PARAM Ro={4*ampl*ampl*K/160e-6}
.PARAM K=1
.lib opamp.sub
.ends rc4200_sq

...
.backanno
.end


Partial netlist after change:
...
.subckt rc4200_sq cos sin Vref Vee out
...
.PARAM Ro={4*ampl*ampl*K/160e-6}
.PARAM K=1
.ends rc4200_sq

....
.inc opamp.sub
.backanno
.end


Hello Ron,
your opamp device is already under "lib&#92;asy&#92;opamps" in the LTSpice
path and the opamp.sub is directly under "lib&#92;sub". So you don't
need it additionally in your working directory.

Best Regards
Helmut

Helmut and Mike,

Many thanks for your help. I moved the Spice directive ".lib
opamp.sub" to the top level as suggested, and the sim ran. It seems
rather awkward to have to remember to put all hierarchical
subcircuit calls at the top level when constructing a hierarchical
schematic, but I guess there's no way around it. (Is there?)

Thanks again,

Ron

--- "rmaxh <rmaxh@y...>" <rmaxh@y...> wrote:

I created a symbol to represent a schematic (symbol
saved as "block"
(.asy)). When I placed it in a higher level
schematic and tried to
run a sim, I got an error message telling me that
subcircuits cannot
be nested. The lower level schematic does have a
subcircuit in it,
and a .lib directive to call that subcircuit, but
this must not be a
limitation of heirarchical schematics, as it would
severely limit
its usefulness. I'm certain I'm doing something
wrong. Anyone know
what that might be?

Ron Harrison

__________________________________________________
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--- In LTspice@..., Panama Mike <panamatex@y...> wrote:

The error message occurs when the schematic
resloves to netlist something like this:

.subckt N1 N2 N3 name1
.subckt N4 N5 N6 name2
[...]
.ends name2
.ends name1

The definition of name2 is inside name1.
Perhaps you have a subcircuit *defined*
in the circuit you want to include a subcircuit.
You can't nest definitions, but there's no
limit on the the depth of the hierarchy.

Hello Mike,

thanks for the tip with the nested subcircuit.
I had the chance to get the circuit files from Ron and remembering
your advice, I immediatly looked into the LTSpice netlist.
It was exactly the problem as you have expected.


Let me sketch the three level hierarchy:

Top: Level-1 schematic: ressitors, instance of level-2

Next Level-2: instance of level-3, resistors, opamp.asy
.include opamp.sub

Next Level-3: transistors, diodes, G-sources


The problem was the ".include opamp.sub" statement in Level-2.
After I moved this statement to the top level-1, the simulation was
possible.


Top: Level-1 schematic: ressitors, instance of level-2
.include opamp.sub

Next Level-2: instance of level-3, resistors, opamp.asy

Next Level-3: transistors, diodes, G-sources



Partial netlist before change:
...
.subckt rc4200_sq cos sin Vref Vee out
...
.PARAM Ro={4*ampl*ampl*K/160e-6}
.PARAM K=1
.lib opamp.sub
.ends rc4200_sq

...
.backanno
.end


Partial netlist after change:
...
.subckt rc4200_sq cos sin Vref Vee out
...
.PARAM Ro={4*ampl*ampl*K/160e-6}
.PARAM K=1
.ends rc4200_sq

....
.inc opamp.sub
.backanno
.end


Hello Ron,
your opamp device is already under "lib&#92;asy&#92;opamps" in the LTSpice
path and the opamp.sub is directly under "lib&#92;sub". So you don't
need it additionally in your working directory.

Best Regards
Helmut

--- "rmaxh <rmaxh@y...>" <rmaxh@y...> wrote:

I created a symbol to represent a schematic (symbol
saved as "block"
(.asy)). When I placed it in a higher level
schematic and tried to
run a sim, I got an error message telling me that
subcircuits cannot
be nested. The lower level schematic does have a
subcircuit in it,
and a .lib directive to call that subcircuit, but
this must not be a
limitation of heirarchical schematics, as it would
severely limit
its usefulness. I'm certain I'm doing something
wrong. Anyone know
what that might be?

Ron Harrison

__________________________________________________
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Yahoo! Mail Plus - Powerful. Affordable. Sign up now.

The error message occurs when the schematic
resloves to netlist something like this:

.subckt N1 N2 N3 name1
.subckt N4 N5 N6 name2
[...]
.ends name2
.ends name1

The definition of name2 is inside name1.
Perhaps you have a subcircuit *defined*
in the circuit you want to include a subcircuit.
You can't nest definitions, but there's no
limit on the the depth of the hierarchy.

--Mike

--- "rmaxh <rmaxh@...>" <rmaxh@...> wrote:

I created a symbol to represent a schematic (symbol
saved as "block"
(.asy)). When I placed it in a higher level
schematic and tried to
run a sim, I got an error message telling me that
subcircuits cannot
be nested. The lower level schematic does have a
subcircuit in it,
and a .lib directive to call that subcircuit, but
this must not be a
limitation of heirarchical schematics, as it would
severely limit
its usefulness. I'm certain I'm doing something
wrong. Anyone know
what that might be?

Ron Harrison

__________________________________________________
Do you Yahoo!?
Yahoo! Mail Plus - Powerful. Affordable. Sign up now.

I created a symbol to represent a schematic (symbol saved as "block"
(.asy)). When I placed it in a higher level schematic and tried to
run a sim, I got an error message telling me that subcircuits cannot
be nested. The lower level schematic does have a subcircuit in it,
and a .lib directive to call that subcircuit, but this must not be a
limitation of heirarchical schematics, as it would severely limit
its usefulness. I'm certain I'm doing something wrong. Anyone know
what that might be?

Ron Harrison

--- In LTspice@..., "polapart <sahawley@m...>"
<sahawley@m...> wrote:

Is there a simple way to convert TI models to run in LTSpice?

Hello,
there are two chances for your opamp models.
The first one is creating a symbol for every opamp type you want to
use. I think this is described in the LTSpice help pages.
The other chance is to make one general symbol. Then you have to
change only the value of the symbol in the schematic.
See my older posting in this group:
Re: Converting PSpice MOSFET models


I recommend to upgrade to the latest LTSpice, version 2.00k at this
writing. It's easier to make symbols/models with the new 2.x release.

Best Regards
Helmut

Dear Mr. Sennewald,

Thank you very much! You gave the final hint to solve the problem! And I already believed in a bug...
As you said, there is no semiconductor device in my circuit. In fact, what you had was the whole circuit... only one line was missing: the line which indicates what library I use. After deleting it, my circuit worked!
I guess, my capacity Cubk (which should mean "C unbekannt" (= "C unknown") ) had the same name as any of my models in a library. I will look for it.

Thank you very much for your help!

Truly Yours

Bernhard

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