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20nm PTM file not working in LTspice

 

I am trying to build 6T SRAM using 20nm but when i run the simulation i am having the errors saying parameter level = 72 and also other bunch of errors.
my 180nm file ran properly but when i tried for 20nm it's not working although i changed W/L ratio from L=0.18 ,W= 0.64 to L= 0.02 to W= 0.3.??
What should i do ?
Re: Switching Speed of a BJT

 

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On 03/04/2025 10:34, Tony Casey wrote:
On 03/04/2025 09:26, jacfev via groups.io wrote:
My question is multiple:
1. What are the influential spice parameters that optimize the switching speed?
To my knowledge, it's mainly Bf that seems to be the most important for increasing the switching speed, which I vary like this:
.step param X LIST 100 150 200 250 300
.model myModel AKO: 2N2222 NPN (Bf={X})
2. What measurement (equation) can be used to measure the speed?
3. What circuit should I use to compare the switching speed results as a function of the influential parameter?
This is not such a simple question. What are your parameters for switching speed? Presumably rise and fall times? How about delays times? You can still have fast rise and fall times, but with a significant delay time if the transistor is driven into saturation.

I would say that Bf is not one of the most influential parameters for speed. More important are the internal capacitances: Cje and Cjc, and transit times: Tf and Tr. Tr sets the reverse recovery time, i.e. charge storage in the base region on switch off - this is critical in saturated BJT switching circuits.

To assess the speed, you need to .MEAS the rise and fall times at the output, and the turn-on and turn-off delay times referenced to the input source waveform.
Testjig uploaded to Files > Temp: BJT_Switching_Speed_Jig.zip

--
Regards,
Tony

Re: Switching Speed of a BJT

 

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I agree with Tony. If Bf is found to affect switching speed, we need to see the test circuit .ASC that you are using, because it's probably not the optimum.

On 2025-04-03 09:34, Tony Casey wrote:
On 03/04/2025 09:26, jacfev via groups.io wrote:
My question is multiple:
1. What are the influential spice parameters that optimize the switching speed?
To my knowledge, it's mainly Bf that seems to be the most important for increasing the switching speed, which I vary like this:
.step param X LIST 100 150 200 250 300
.model myModel AKO: 2N2222 NPN (Bf={X})
2. What measurement (equation) can be used to measure the speed?
3. What circuit should I use to compare the switching speed results as a function of the influential parameter?
This is not such a simple question. What are your parameters for switching speed? Presumably rise and fall times? How about delays times? You can still have fast rise and fall times, but with a significant delay time if the transistor is driven into saturation.

I would say that Bf is not one of the most influential parameters for speed. More important are the internal capacitances: Cje and Cjc, and transit times: Tf and Tr. Tr sets the reverse recovery time, i.e. charge storage in the base region on switch off - this is critical in saturated BJT switching circuits.

To assess the speed, you need to .MEAS the rise and fall times at the output, and the turn-on and turn-off delay times referenced to the input source waveform.

--
Regards,
Tony
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Re: CD4000 test

 

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On 03/04/2025 09:55, eewiz via groups.io wrote:
Gentlemen, those CD4x and 74HC libraries have two required values that appear on a symbol's SpiceModel line.
ctrl-right-click a logic symbol to alter its SpiceModel line.
By default the two values are the nodes "VDD" and "0".
Creating a 12V power supply for CD4x logic and naming its output node VDD works out-of-the-box.
But assume for example, you already have a V-24 node and a V-12 node that could power the logic.
Change the logic symbol's default SpiceModel value from "VDD 0" to "V-12 V-24".
This sets logic outputs to be V(V-12)=logic-high and V(V-24)=logic-low, instead of VDD/0.
?
In either case the difference across the power pins is 12 volts, -12 to -24 volts or 12 to 0 volts has the same 12 volt difference.
To power the internal logic from 12 volts, change the symbol's default SpiceLine (not SpiceModel) value from VDD=5 to VDD=12.
The SpiceLine VDD=x value sets the model's power-pin voltage and can be anything like VDD=2.3 or 3.5, 6, 12 etc...
The three SpiceLine values control functions within the logic like, prop-delay, output drive, slew rate, etc...
The SpiceLine SPEED=1.0 and TRIPDT=5e-9 are defaulted for the logic family.
?
Changing the VDD=x value affects the speed of a given device. (i.e. CD4x is much faster at 15V than it is at 5V)
The SpiceLine SPEED=1.0 value is relative.
To model CD4x-like logic at 12 volts that is 10 times faster than normal CD4x logic, change the SpiceLine SPEED=1.0 value to SPEED=10.
This is not quite correct. The CD4000 parts do have the internal "VDD" supply node, but in the 74HC parts, it is "VCC".

--
Regards,
Tony
Re: Switching Speed of a BJT

 

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On 03/04/2025 09:26, jacfev via groups.io wrote:
My question is multiple:
1. What are the influential spice parameters that optimize the switching speed?
To my knowledge, it's mainly Bf that seems to be the most important for increasing the switching speed, which I vary like this:
.step param X LIST 100 150 200 250 300
.model myModel AKO: 2N2222 NPN (Bf={X})
2. What measurement (equation) can be used to measure the speed?
3. What circuit should I use to compare the switching speed results as a function of the influential parameter?
This is not such a simple question. What are your parameters for switching speed? Presumably rise and fall times? How about delays times? You can still have fast rise and fall times, but with a significant delay time if the transistor is driven into saturation.

I would say that Bf is not one of the most influential parameters for speed. More important are the internal capacitances: Cje and Cjc, and transit times: Tf and Tr. Tr sets the reverse recovery time, i.e. charge storage in the base region on switch off - this is critical in saturated BJT switching circuits.

To assess the speed, you need to .MEAS the rise and fall times at the output, and the turn-on and turn-off delay times referenced to the input source waveform.

--
Regards,
Tony

Re: CD4000 test

 

Gentlemen, those CD4x and 74HC libraries have two required values that appear on a symbol's SpiceModel line.
ctrl-right-click a logic symbol to alter its SpiceModel line.
By default the two values are the nodes "VDD" and "0".
Creating a 12V power supply for CD4x logic and naming its output node VDD works out-of-the-box.
But assume for example, you already have a V-24 node and a V-12 node that could power the logic.
Change the logic symbol's default SpiceModel value from "VDD 0" to "V-12 V-24".
This sets logic outputs to be V(V-12)=logic-high and V(V-24)=logic-low, instead of VDD/0.
?
In either case the difference across the power pins is 12 volts, -12 to -24 volts or 12 to 0 volts has the same 12 volt difference.
To power the internal logic from 12 volts, change the symbol's default SpiceLine (not SpiceModel) value from VDD=5 to VDD=12.
The SpiceLine VDD=x value sets the model's power-pin voltage and can be anything like VDD=2.3 or 3.5, 6, 12 etc...
The three SpiceLine values control functions within the logic like, prop-delay, output drive, slew rate, etc...
The SpiceLine SPEED=1.0 and TRIPDT=5e-9 are defaulted for the logic family.
?
Changing the VDD=x value affects the speed of a given device. (i.e. CD4x is much faster at 15V than it is at 5V)
The SpiceLine SPEED=1.0 value is relative.
To model CD4x-like logic at 12 volts that is 10 times faster than normal CD4x logic, change the SpiceLine SPEED=1.0 value to SPEED=10.
?
All for now
?

Sent:?Wednesday, April 02, 2025 at 12:52 PM
From:?"Andy I via groups.io" <AI.egrps+io@...>
To:[email protected]
Subject:?Re: [LTspice] CD4000 test
On Wed, Apr 2, 2025 at 12:38 PM, DerekK wrote:
As for the circuit, I played some more but cannot get the output of the CD4013B to change. Both Q and Q* are staying at zero on the first stage when I am running a clock on the input. I even played with changing values of SET and RST with no change in the output. Something should be moving.
Your voltage source V2 drives node VDD1.? ?That? should be node VDD.? ?These CD4000 models require a power node named "VDD".
?
Andy
?
Switching Speed of a BJT

 

Hello,
My question is multiple:
1. What are the influential spice parameters that optimize the switching speed?
To my knowledge, it's mainly Bf that seems to be the most important for increasing the switching speed, which I vary like this:
.step param X LIST 100 150 200 250 300
.model myModel AKO: 2N2222 NPN (Bf={X})
2. What measurement (equation) can be used to measure the speed?
3. What circuit should I use to compare the switching speed results as a function of the influential parameter?
Re: CD4000 test

 

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Those messages are not significant LTspice error messages. They are probably due to over-keen syntax checks that were introduced in some 24.1.x versions of LTspice. I don't see them in my .LOG file, which is not a surprise, because they include a path that only exists on your computer. Which version of LTspice are you using?

I can't see why you can't probe the circuit, of course, but you can't probe pins that have no wire attached. Can you plot the voltage on the wire connected to Qbar of U2, for example?

On 2025-04-02 16:20, DerekK wrote:
At the end of the log file I get the following and cannot probe the circuit. I know it is a short run-time circuit. It is a portion of a larger one, and I have not played with the digital stuff before.
----------------------------
T:\Other drawings\XM27 gun\41897800 Elec Sys Assy\41897801 Ctl Box\41897802 Control box\41897817 K3 Relay assy\A154\simulation\cd4000_v.lib(91): syntax error
.param td1=1e-9*(400-40-10)*5.0/(vdd1}*{speed1}
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^
T:\Other drawings\XM27 gun\41897800 Elec Sys Assy\41897801 Ctl Box\41897802 Control box\41897817 K3 Relay assy\A154\simulation\cd4000_v.lib(92): Expected ")" here.
.param td2=1e-9*(250-40-10)*5.0/(vdd1}*{speed1}
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^
T:\Other drawings\XM27 gun\41897800 Elec Sys Assy\41897801 Ctl Box\41897802 Control box\41897817 K3 Relay assy\A154\simulation\cd4000_v.lib(92): syntax error
.param td2=1e-9*(250-40-10)*5.0/(vdd1}*{speed1}
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^
T:\Other drawings\XM27 gun\41897800 Elec Sys Assy\41897801 Ctl Box\41897802 Control box\41897817 K3 Relay assy\A154\simulation\cd4000_v.lib(93): Expected ")" here.
.param td4=1e-9*(130-40-10)*5.0/(vdd1}*{speed1}
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^
T:\Other drawings\XM27 gun\41897800 Elec Sys Assy\41897801 Ctl Box\41897802 Control box\41897817 K3 Relay assy\A154\simulation\cd4000_v.lib(93): syntax error
.param td4=1e-9*(130-40-10)*5.0/(vdd1}*{speed1}
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^
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Re: CD4000 test

 

It was the VDD1 that was the final issue. Now things are moving correctly. Thanks all for the support.
Re: CD4000 test

 

Derek,
?
I am curious whether there is a purpose to the 0.001 uF capacitor (C1) on the Q output of the last CD4013, U4?
?
Also, I assume you know node RST is floating, in the simulations you uploaded.
?
Andy
?
Re: CD4000 test

 

Also, the parameter name in the top-level schematic should be "VDD", not "VDD1".? And the parameter "Speed1" on the top-level schematic should have been named "Speed", but it was set to the default value anyway so it would not have done anything.
?
I don't know how that was changed, or why you changed it.? If I remember correctly, those CD4000 models use names such as "VDD1" internally, but the top-level names must be without the "1" added.? The library file passes the value from VDD to VDD1.
?
Andy
?
?
Re: CD4000 test

 

On Wed, Apr 2, 2025 at 12:38 PM, DerekK wrote:
As for the circuit, I played some more but cannot get the output of the CD4013B to change. Both Q and Q* are staying at zero on the first stage when I am running a clock on the input. I even played with changing values of SET and RST with no change in the output. Something should be moving.
Your voltage source V2 drives node VDD1.? ?That? should be node VDD.? ?These CD4000 models require a power node named "VDD".
?
Andy
?
Re: CD4000 test

 

OK, found the proper lib as well. Had to sort by date. We should get rid of the old stuff so that others do not download items in error.
?
As for the circuit, I played some more but cannot get the output of the CD4013B to change. Both Q and Q* are staying at zero on the first stage when I am running a clock on the input. I even played with changing values of SET and RST with no change in the output. Something should be moving.
?
Uploaded as CD_test.v3.zip. I have the .lib, .asy, .asc and .plt file included.
?
Re: CD4000 test

 

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On 02/04/2025 17:47, DerekK wrote:
Found it!!! It actually was an error in the .lib file. There are a few instances of "(vdd1" which should have a different bracket: "{vdd1". Now it runs. And this was from the recent download suggested.
This precise error came up here recently.The fact that you got an error shows you must be running LTspice V24.1.x. This "error" has been in the library since the beginning, but previous versions of LTspice didn't flag it and allowed it to proceed.

eetech00 uploaded a fixed library that you presumably didn't find: CD4000_v(65a).lib on Feb 21 2025.

--
Regards,
Tony
Re: CD4000 test

 

Derek,
?
Those errors depend on which version of LTspice you are using.
?
On older versions, there are no errors in the Error Log file.? It simulates "correctly" and produces the right waveforms - though you really need for the simulation time to be longer to see more action.? There are several status messages and a few warnings, but none of them are errors.
?
The error messages that you saw are the result of using the latest LTspice versions (v24.1.*) which are quite a bit more picky about syntax, than all prior versions were.? This might be considered one case where having the newest LTspice version is not to your advantage - although that is debatable.? In fact, there probably were mistakes in the library file, which had gone undetected for several years.
?
Andy
?
?
Re: CD4000 test

 

Found it!!! It actually was an error in the .lib file. There are a few instances of "(vdd1" which should have a different bracket: "{vdd1". Now it runs. And this was from the recent download suggested.
Re: CD4000 test

 

At the end of the log file I get the following and cannot probe the circuit. I know it is a short run-time circuit. It is a portion of a larger one, and I have not played with the digital stuff before.
----------------------------
C:\Users\derek\Desktop\New folder\cd4000_v.lib(91): syntax error
.param td1=1e-9*(400-40-10)*5.0/(vdd1}*{speed1}
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^
C:\Users\derek\Desktop\New folder\cd4000_v.lib(92): Expected ")" here.
.param td2=1e-9*(250-40-10)*5.0/(vdd1}*{speed1}
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^
C:\Users\derek\Desktop\New folder\cd4000_v.lib(92): syntax error
.param td2=1e-9*(250-40-10)*5.0/(vdd1}*{speed1}
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^
C:\Users\derek\Desktop\New folder\cd4000_v.lib(93): Expected ")" here.
.param td4=1e-9*(130-40-10)*5.0/(vdd1}*{speed1}
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^
C:\Users\derek\Desktop\New folder\cd4000_v.lib(93): syntax error
.param td4=1e-9*(130-40-10)*5.0/(vdd1}*{speed1}
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^
?
Re: CD4000 test

 

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You uploaded the .LIB file twice, instead of the .LOG file, but there was no need anyway, we can run the sim to get the .LOG file. The sim runs OK (but does it do what you want? It seems to be a short time sim.), and those Warnings in the .LOG can be disregarded: the nodes probably connect to current sources, which have infinite impedance, so don't register as connected.

On 2025-04-02 15:31, DerekK wrote:
Andy,
I updated the symbol from the suggested source. Deleted the old symbol and placed the new one. Restarted LTSpice. Still getting errors. I re-uploaded the CD_test.zip file. This time I included the log file which shows the error.
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Re: CD4000 test

 

Andy,
I updated the symbol from the suggested source. Deleted the old symbol and placed the new one. Restarted LTSpice. Still getting errors. I re-uploaded the CD_test.zip file. This time I included the log file which shows the error.
Re: creating PNP caracteristicsby sweeping plot in LTspice from a circuit I built

 

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On 02/04/2025 13:59, john23 via groups.io wrote:
Hello Andy,I have taken your circuit and changed the current source into voltage source ,also Imade the voltage potential the same way put the voltage source in the collector.
I got a very close plot to what you got but the slope of the active mode is much higher.
Why is my slope shown in the attached photo much higher with respect to what you done?
You circuit is completely messed up. If you wanted to reproduce Andy's plot, why didn't you use his circuit? To get the characteristic in a datasheet, you need to exactly use the conditions quoted in the datasheet. Don't introduce spurious resistors that are not in the test circuit that the manufacturers used.

Please check: PNP_OP_Chacteristic.zip

--
Regards,
Tony

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