Also, the parameter name in the top-level schematic should be "VDD", not "VDD1".? And the parameter "Speed1" on the top-level schematic should have been named "Speed", but it was set to the default value anyway so it would not have done anything.
?
I don't know how that was changed, or why you changed it.? If I remember correctly, those CD4000 models use names such as "VDD1" internally, but the top-level names must be without the "1" added.? The library file passes the value from VDD to VDD1.
?
Andy
?
?
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On Wed, Apr 2, 2025 at 12:38 PM, DerekK wrote:
As for the circuit, I played some more but cannot get the output of the CD4013B to change. Both Q and Q* are staying at zero on the first stage when I am running a clock on the input. I even played with changing values of SET and RST with no change in the output. Something should be moving.
Your voltage source V2 drives node VDD1.? ?That? should be node VDD.? ?These CD4000 models require a power node named "VDD".
?
Andy
?
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OK, found the proper lib as well. Had to sort by date. We should get rid of the old stuff so that others do not download items in error.
?
As for the circuit, I played some more but cannot get the output of the CD4013B to change. Both Q and Q* are staying at zero on the first stage when I am running a clock on the input. I even played with changing values of SET and RST with no change in the output. Something should be moving.
?
Uploaded as CD_test.v3.zip. I have the .lib, .asy, .asc and .plt file included.
?
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On 02/04/2025 17:47, DerekK wrote:
Found it!!! It
actually was an error in the .lib file. There are a few instances
of "(vdd1" which should have a different bracket: "{vdd1". Now it
runs. And this was from the recent download suggested.
This precise error came up here recently.The fact that you got an
error shows you must be running LTspice V24.1.x. This "error" has
been in the library since the beginning, but previous versions of
LTspice didn't flag it and allowed it to proceed.
eetech00 uploaded a fixed library that you presumably didn't find: CD4000_v(65a).lib
on Feb 21 2025.
--
Regards,
Tony
|
Derek,
?
Those errors depend on which version of LTspice you are using.
?
On older versions, there are no errors in the Error Log file.? It simulates "correctly" and produces the right waveforms - though you really need for the simulation time to be longer to see more action.? There are several status messages and a few warnings, but none of them are errors.
?
The error messages that you saw are the result of using the latest LTspice versions (v24.1.*) which are quite a bit more picky about syntax, than all prior versions were.? This might be considered one case where having the newest LTspice version is not to your advantage - although that is debatable.? In fact, there probably were mistakes in the library file, which had gone undetected for several years.
?
Andy
?
?
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Found it!!! It actually was an error in the .lib file. There are a few instances of "(vdd1" which should have a different bracket: "{vdd1". Now it runs. And this was from the recent download suggested.
|
At the end of the log file I get the following and cannot probe the circuit. I know it is a short run-time circuit. It is a portion of a larger one, and I have not played with the digital stuff before.
----------------------------
C:\Users\derek\Desktop\New folder\cd4000_v.lib(91): syntax error
.param td1=1e-9*(400-40-10)*5.0/(vdd1}*{speed1} ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^ C:\Users\derek\Desktop\New folder\cd4000_v.lib(92): Expected ")" here. .param td2=1e-9*(250-40-10)*5.0/(vdd1}*{speed1} ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^ C:\Users\derek\Desktop\New folder\cd4000_v.lib(92): syntax error .param td2=1e-9*(250-40-10)*5.0/(vdd1}*{speed1} ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^ C:\Users\derek\Desktop\New folder\cd4000_v.lib(93): Expected ")" here. .param td4=1e-9*(130-40-10)*5.0/(vdd1}*{speed1} ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^ C:\Users\derek\Desktop\New folder\cd4000_v.lib(93): syntax error .param td4=1e-9*(130-40-10)*5.0/(vdd1}*{speed1} ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^
?
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You uploaded the .LIB file twice, instead of
the .LOG file, but there was no need anyway, we can run the sim
to get the .LOG file. The sim runs OK (but does it do what you
want? It seems to be a short time sim.), and those Warnings in
the .LOG can be disregarded: the nodes probably connect to
current sources, which have infinite impedance, so don't
register as connected.
On 2025-04-02 15:31, DerekK wrote:
Andy,
I updated the symbol from the suggested source. Deleted the
old symbol and placed the new one. Restarted LTSpice. Still
getting errors. I re-uploaded the CD_test.zip file. This time I
included the log file which shows the error.
--
OOO - Own Opinions only
If something is true:
* as far as we know - it's science
*for certain - it's mathematics
*unquestionably - it's religion
|
Andy,
I updated the symbol from the suggested source. Deleted the old symbol and placed the new one. Restarted LTSpice. Still getting errors. I re-uploaded the CD_test.zip file. This time I included the log file which shows the error.
|
Re: creating PNP caracteristicsby sweeping plot in LTspice from a circuit I built
On 02/04/2025 13:59, john23 via
groups.io wrote:
Hello Andy,I have taken your circuit and changed the current
source into voltage source ,also Imade the voltage potential the
same way put the voltage source in the collector.
I got a very close plot to what you got but the slope of the
active mode is much higher.
Why is my slope shown in the attached photo much higher with
respect to what you done?
You circuit is completely messed up. If you wanted to reproduce
Andy's plot, why didn't you use his circuit? To get the
characteristic in a datasheet, you need to exactly use the
conditions quoted in the datasheet. Don't introduce spurious
resistors that are not in the test circuit that the manufacturers
used.
Please check: PNP_OP_Chacteristic.zip
--
Regards,
Tony
|
Re: creating PNP caracteristicsby sweeping plot in LTspice from a circuit I built
This might help answer your question:
?
Why is my slope shown in the attached photo much higher with respect to what you done?
The slope is greater because of V1 and R2.? ?As the voltage from V1 increases, Vc increases almost the same because the transistor is in saturation.? Ohm's law applied to R2 gives you the slope.
?
Andy
?
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Re: creating PNP caracteristicsby sweeping plot in LTspice from a circuit I built
On Wed, Apr 2, 2025 at 07:59 AM, john23 wrote:
Hello Andy,I have taken your circuit and changed the current source into voltage source ,also Imade the voltage potential the same way put the voltage source in the collector.
Why do you want to modify the circuit?
?
What is the purpose of adding resistors, and changing the base drive from a stepped current source to a voltage that also depends on Vce?
?
I think you need to answer these questions before thinking about the results with your circuit.? For what purpose are you doing this?? Are you doing it just to ask annoying questions, or do you have an actual goal in mind?? Without that, your questions seem meaningless and without purpose.
?
I got a very close plot to what you got but the slope of the active mode is much higher.
Why is my slope shown in the attached photo much higher with respect to what you done?
Look at your circuit, and what you have done to it.
?
You added resistance to the transistor.? Resistance changes the slopes.
?
You applied the base drive between the base and ground, while simultaneously sweeping the emitter voltage.? Therefore, as the emitter voltage increases, the base-emitter voltage also increases (negatively), turning ON the transistor much much harder.? By the time V1 reaches 5 V, the base-emitter voltage in your circuit exceeds -1.6 V which means the transistor is being turned ON extremely hard.? The base current is unusually large for a small-signal transistor and it is fully saturated over most of the sweep range.
?
Your circuit makes no sense to me.? Please explain the function of your circuit.? Did you plan it, or did you arbitrarily connect some components?? Please help me understand why you did this.
?
Andy
?
|
Re: creating PNP caracteristicsby sweeping plot in LTspice from a circuit I built
Hello Andy,I have taken your circuit and changed the current source into voltage source ,also Imade the voltage potential the same way put the voltage source in the collector.
I got a very close plot to what you got but the slope of the active mode is much higher.
Why is my slope shown in the attached photo much higher with respect to what you done?
Thanks.
|
Here is your problem.? You either obtained a bad copy of your symbol file CD4013B.asy, or you (or someone in your group) modified it, and that's causing that error.
?
Download this file:?
Files > z_yahoo > Lib > Digital CD4000 > CD4000.zip
then either unzip it, or pull out just the one file (CD4013B.asy) that you need.? Use that instead of the symbol file you were using.? Depending on where you put your files, you might need to overwrite or delete the old file.
?
You might also need to delete the symbols from your schematic (Draft2.asc) and then add them back again.? There are some Attributes that are "sticky" and remain in the schematic even if the attribute in the symbol changes.? Deleting and re-adding the symbol takes care of that.
?
If this does not fix the problem, then ask again.? Your message said "errors" (plural) but did not say what they were.? So I am left wondering what error or errors you had.
?
Andy
?
?
?
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On Tue, Apr 1, 2025 at 08:34 PM, DerekK wrote:
I am trying to work with the CD4000_v.lib and am getting errors when trying to run. Would someone provide me some guidance as to what is set up in error?
The error I get is:
Fatal Error: Could not open library file "CD4000.LIB"
That happens because the symbol cd4013b.asy attempts to load the library file CD4000.lib, whereas your simulation only has CD4000_v.lib.
?
Where exactly did that symbol file come from?? Did you download it from the same location (in our group's files) where the library files are?
?
Andy
?
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I am trying to work with the CD4000_v.lib and am getting errors when trying to run. Would someone provide me some guidance as to what is set up in error?
?
File uploaded to temp: CD_test.zip
?
This is using the CD4013 as a counter. I have included the latest CD4000_v.lib and the CD4013B symbol from the files section to make it easy.
|
Re: Simulation runs very slowly: test.asc
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Re: creating PNP caracteristicsby sweeping plot in LTspice from a circuit I built
On Tue, Apr 1, 2025 at 02:20 PM, john23 wrote:
Hello,I would like to try and implement the caracteristics with the circuit I made (attached)
Do you wish to sweep the curves of this one unique circuit?? Or do you wish to sweep the curves of a PNP transistor?
?
If you want to plot curves of this one unique circuit, then first you need to know what are the curves that you want to sweep.? What properties of this one circuit do you want to see in a plot?
?
PNP have current structure where we can see by the current slope that PNP is saturated or linear.
How can we create such current plot?
See my circuits in "PNP_sweep.zip" in the Temp folder.? They plot the Ic/Ib and Ic/Vbe curves for just the PNP transistor.? The Ic/Ib plot is the one you most often see, because the transfer from Vbe to Ic is strongly nonlinear.? The Ic/Ib plot is also the one that corresponds to your photo "2.png" that you uploaded yesterday inside your "31_03_25.zip".
?
Andy
?
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Re: creating PNP caracteristicsby sweeping plot in LTspice from a circuit I built
Your message is confused, your.ASC is
unsuitable. Looking at currents will not tell you about
saturation, which is when Vce drops to a very low value, like
0.4 V or less. It never does that in your .ASC.
On 2025-04-01 19:20, john23 via
groups.io wrote:
Hello,I would like to try and implement the caracteristics
with the circuit I made (attached)
By sweeping V1 (emitter source I see 0 current increases
after Vbe>0.7)
Hopwever I cant see if the PNP is in saturation or linear
states.
PNP have current structure where we can see by the current slope
that PNP is saturated or linear.
How can we create such current plot?
Thanks.?
?
--
OOO - Own Opinions only
If something is true:
* as far as we know - it's science
*for certain - it's mathematics
*unquestionably - it's religion
|
Re: creating PNP caracteristicsby sweeping plot in LTspice from a circuit I built
Hello,I would like to try and implement the caracteristics with the circuit I made (attached)
By sweeping V1 (emitter source I see 0 current increases after Vbe>0.7)
Hopwever I cant see if the PNP is in saturation or linear states.
PNP have current structure where we can see by the current slope that PNP is saturated or linear.
How can we create such current plot?
Thanks.?
?
/g/LTspice/files/Temp/Draft2%20%281%29.zip
|
DerekK
Tony Casey
John Woodgate