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Looking for advice on TRAN timing
#FFT
I'm looking for help concerning the timing parameters of a TRAN simulation
to evaluate the distortion of an amplified sine wave.
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I've been reading through lots of messages of this group concerning "distortion" and "tran timing"
recently but could not find an answer to what I was looking for.
[I came across the audio distortion analyser contributed by Tony Casey, for which I am thankful and it is indeed a fine tool.]
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Hitherto I've used 1 or 2 per mille of the sine wave period, so the time step would be 1 usec or 2 usec
when testing with 1 kHz. From my tests I decided for myself that values exceeding 1% of the period
should best be avoided.
I also tested time steps adjusted to the power of 2, e.g. 2**14 (interval / 16384).? ?
For the interval (t_stop - t_start) I usually take 16msec when testing with 1kHz
but I have also used values from 10msec to 48msec.
It is this parameter which I personally find most difficult to decide upon.
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So, to sum it all up, I wonder if there is a guideline which values to use for the time step
and the interval for a certain test frequency when testing audio related circuits with sine waves.
(I'm still using LTspice XVII.)
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Ryu
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Re: 12AU7 tube heater model
On Fri, Feb 21, 2025 at 03:50 AM, Carlo wrote:
This is a "false" error, coming from processing the topology of the model.? I think you can safely ignore it. ?
This model uses a G-source to emulate a variable resistance.? That is a popular technique among SPICE model-makers.? The problem is that a G-source is a controlled current source.? However, note that the G-source:
includes the voltage between its own output terminals, V(HB,H2), in its formula, thereby turning it into a resistor, not an ideal current source.? But LTspice doesn't know this.? It sees the circuit topology as a current source connected to another current source, and it thinks the node where they join is "floating".? So it generates the error message, but it continues to process the netlist anyway, and everything works!
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It works OK because Ghot emulates a resistor, and that node is not really floating.? But that is a difficult thing to figure out, and there is no suggestion of that from the topology alone.? The error message comes from the topology check.
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My advice?? Ignore that error message.? We see it a lot in models that use G-sources to emulate controllable resistors.? I think it's the most "compatible" way of making a variable resistor.? But the "error" is harmless because it's not real.
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Andy
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Re: LTspice Save Internal Device Voltages
On Fri, Feb 21, 2025 at 04:12 AM, Andy I wrote:
It might be that the internal node in the Thevenin equivalent of a lossless inductor is not one of them either.Thinking again about it, since Thevenin equivalent introduces actually the inductor current as new system's unknown, maybe it doesn't count as new "internal node voltage" though. ?
Carlo. |
Re: LTspice Save Internal Device Voltages
I never knew exactly what those "internal device" nodes were, and I think it was never explained, in the years I have been following this group.
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I suspect those internal nodes might be internal to certain transistor models.? For example, if you look at the VBIC model, the circuit is quite complex and has a handful of what appear to be internal nodes.? I tried once to see if those were the "internal device" nodes that this setting refers to, but was unable to see them.? It might be that the internal node in the Thevenin equivalent of a lossless inductor is not one of them either.
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Andy
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LTspice Save Internal Device Voltages
On LTspice Control Panel->Save Default tab there is a checkbox named "Save Internal Device Voltages".
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I believe it is supposed to save the voltages of "device internal nodes". Take for instance an inductor with a default Rser=1m. For a such device, LTspice employs a proprietary "compound model" based on Norton equivalent in order to reduce the overall circuit's solving matrix size.
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As explained in Help page, setting Rser=0 forces LTspice to use the "cumbersome" Thevenin equivalent introducing an internal node in the inductor's model. That means the current through the inductor becomes a new unknown of the circuit's solving system (you can check this in SPICE Error log: the matrix size actually increments by 1).
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That said, I thought the checkbox above added some information about this "device internal node". However, it seems it is not actually the case.
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Any idea about it ? Thanks.
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Carlo.
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Re: 12AU7 tube heater model
¿ªÔÆÌåÓýSorry, I misinterpreted that last line in the
netlist. A G source is a voltage-dependent current source, so it
defines a transconductance, not a simple conductance. I think
that the syntax in the Help is much too terse: the parameter N
is, for example, not defined, and it seems that it is not
essential to use the old POLY command. On 2025-02-21 10:27, Carlo wrote:
--
OOO - Own Opinions only If something is true: * as far as we know - it's science *for certain - it's mathematics *unquestionably - it's religion |
Re: Interpreting Noise Simulation Results
¿ªÔÆÌåÓýFurther to what I wrote below, I have uploaded a modified version of your schematic that uses a single amplifier circuit but switches the filter networks into or of out of circuit. This enables the noise with and without the HPFs to be displayed on the same graph, by stepping the Ctl parameter.You should also know that the FMMT718 model you have added is unreasonably optimistic, as it exhibits no 1/f noise. In any event it is swamped by the increased noise from the HPFs, when these are in circuit. You could drastically decrease the noise contribution of the HPFs by scaling the impedance down, while keeping the cut-off frequency the same. I've shown the effect of changing Rfilt from 100¦¸ to 10k¦¸. -- Regards,
Tony On 20/02/2025 23:19, Tony Casey wrote:
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Re: 12AU7 tube heater model
On Fri, Feb 21, 2025 at 01:59 AM, John Woodgate wrote:
I suspect that the 'error message' is nothing to worry about. the current source has infinite impedance, so the U1:HB node appears not to be connected.Sorry, what kind of controlled source is actually the G source named "hot" within the SUBCKT heater model ? ?
From LTspice help:
Does it mean that Ghot is just a behavioral voltage source, or that it is a current source controlled from a voltage (i.e. voltage-controlled current source) ?
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Re: 3 Phase Voltage Sense model
¿ªÔÆÌåÓýFor curiosityWhat device are you driving with Vout(ABC) ? My home is "3Phased"? :) Le 20/02/2025 ¨¤ 18:58,
larry.gunseor@... a ¨¦crit?:
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Re: 12AU7 tube heater model
¿ªÔÆÌåÓýI suspect that the 'error message' is nothing
to worry about. the current source has infinite impedance, so
the U1:HB node appears not to be connected. RHO=42 means that
the heater is set for 12.6V/0.15A operation, whereas the amp
circuit may be using either 6.3V/0.3A or 6.3V/0.3A. The bad
behaviour of the amp circuit must be due to the last line of the
heater netlist, since that function returns an infinite value at
start-up, where V(HB,H2) = 0. I don't see what that conductance
represents anyway, nor why it's defined as a conductance rather
than a resistance. The whole thing looks very complicated for
representing a simple hot wire. On 2025-02-21 08:50, Carlo wrote:
--
OOO - Own Opinions only If something is true: * as far as we know - it's science *for certain - it's mathematics *unquestionably - it's religion |
Re: 3 Phase Voltage Sense model
¿ªÔÆÌåÓýSymbol pin order is good with "3Phase_Voltage_Sense.asy"Delete "3Phase_Voltage_Sense.asy" Load "3Phase_Voltage_Sense_model.asc" Generate "3Phase_Voltage_Sense_model.asy" by clicking "Hierarchy/Open or generate ..? " Load "3Phase_Voltage_Sense_Test.asc" Place "3Phase_Voltage_Sense_model.asy" And yes, pin order has changed, correct cabling And it works Ground to Neutral is necessary "3Phase_Vsense.sub" is unuseful Greetings Le 21/02/2025 ¨¤ 06:53, Andy I via
groups.io a ¨¦crit?:
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12AU7 tube heater model
Starting from the 12AU7 SUBCKT from , I created a SUBCKT model for the 12AU7 heater, namely:
I used it in a simple schematic doing a DC Sweep analysis on a DC current source connected to heater's pins H1 and H2 (one of the current source's pin is connected to GND). However Spice Error log reports the following:
What is the problem behind it ? Thanks.
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Carlo. |
Re: PWM Timing Causing Shoot-thru
May,
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I don't know if we will see your updated file with the missing LTspice symbol, or if you consider the problem to be solved already.
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But I want to mention that your signals HCF and LCF did not look right.? In contrast with the other two pairs which have no overlap, the HCF and LCF pair have tons of overlap.? I think maybe you forgot to invert one of them.? Maybe that is correct, but it looks funny when compared with the other two pairs.
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Andy
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Re: 3 Phase Voltage Sense model
Larry,
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Here is an actual mistake, and the likely cause of the problem you have.? The pin-order of the symbol does not match the pin-order of the included netlist model.
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Symbol's pin-order:? Neutral VinA VinB VinC VoutA VoutB VoutC
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Subcircuit's pin-order:? VinA VinB VinC Neutral VoutA VoutB VoutC
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That needs to be corrected.? Edit either the symbol (.asy) file or the model (.sub) file.
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Andy
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Re: 3 Phase Voltage Sense model
Larry,
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Here are some issues to comment on:
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(1)? Your original schematic (3Phase_Voltage_Sense_circuit.asc) leaves the Neutral net floating.? Why?? Did you really want it to float like that?? Also, do you want it grounded in the final schematic?? If nothing else, it is different.
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(2)? The symbol you created (3Phase_Voltage_Sense.asy) is set up with incorrect properties.? It should have Symbol Type = Cell, but you left it with Symbol Type = Block, which is correct only for calling a lower-level schematic, not a netlist file.? Fortunately LTspice seems to handle it anyway in spite of the wrong property.
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(3)? Your final schematic (3Phase_Voltage_Sense_Test.asc) should not have ".inc 3Phase_Vsense.sub" because the symbol file already includes that netlist file.? It does not actually hurt because the end result is that the subcircuit file is included twice.? But it's not a good idea to do that because it might later create problems.
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I think none of these issues causes the problem you have, but I want to mention them anyway.
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Andy
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Locked
Re: Windows XP installation disk
Off-topic.? And it suggests it is not legal.
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This topic is closed.? No replies, please.
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This group is about LTspice. |
Locked
Windows XP installation disk
Does anyone have a Windows XP install disk they could give or sell me? ?Or a copy with the password decrypted. ? I need a pukka XP machine to run the software I wrote myself in da last Millenium. ?Yes. ?I've tried the various Virtual machines but none of them give me the functionality I need. ?To put this into perspective, I run a DOS window under Win 98 on the XP machine. ? Machines that have XP drivers are all more than 10 yrs old. ?I found one but I lent my pukka XP install disc to a friend who promptly lost it?? |
Re: Weird results DC operating point for Tube amplifier
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Show quoted text
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CD4000_v(65).lib with syntax error messages updated to CD4000_v(65a).lib
hi
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I've corrected and uploaded CD4000_v(65a).lib
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The only corrections made were to the td1,td2,td4 equations used in CD4008B sub circuit.
The unbalanced braces/parenths caused syntax error messages in LTspice 24.1.4
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eetech00 |