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Auto loadbias and savebias for stepped simulations
I recently asked Mike if would be possible to add a new feature to .savebias and .loadbias invoked by the keyword ¡°eachstep¡± whereby in a stepped simulation, each succeeding step would load the bias saved by the preceding step.? Among other uses, this could allow eliminating the startup transient between steps when performing a time domain frequency response analysis. Currently bias data may be saved from individual steps, but the syntax is cumbersome as each step must be specified: .savebias bias1.txt time=1m step=0 Unfortunately, there is no way to load different bias data for steps, which is the reason for my request to Mike.
.subckt L 1 2 .param L=1 Rser=1m Rpar=1/Gmin C1 3 0 {L} Rser={1/Rpar} Rpar={1/Rser} G1 1 2 3 0 1 G2 3 0 2 1 1 .ends L ? Merry Christmas and a Happy New Year |
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Re: What does Heightened Def Con mean ?
wgrandner wrote, "What does Heightened Def Con mean ?" It means LTspice is having some trouble, but hasn't given up yet. In your case, it may mean there is something in your circuits that is making LTspice unhappy. Here is a very old message, from the master himself (LTspice's author): ? ?? ? ? Def Con" comes from the term DEFCON or DEFense CONdition. ? ? In public service, this runs from 5 to 1. The lowest state ? ? of defensive readiness is condition 5, meaning normal ? ? peacetime. DEFCON 1 is the highest defensive condition ? ? readiness and means the country is at war. ? ? In LTspice, the scale is reversed, Def Con 0 means it's ? ? having no trouble solving the circuit and increases with ? ? circuit difficulty. Its main use for macro models circuits ? ? is to let you gauge a bit as to how robust the model is. ? ? I haven't looked at your circuit, bit it sounds like you ? ? might be exciting some some kind of a race condition in the ? ? model. Don't forget to try the alternate solver when you ? ? have convergence problems. ? ? --Mike Note the mention of the Alternate Solver.? It might (or might not) help eliminate those messages.? The Alternate Solver is usually more accurate, but slower; but in some cases it can be the other way around.? Don't forget that the Alternate Solver is a "sitcky" setting, so it remains selected until you un-select it. Regards, Andy |
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Re: Is it possible to dynamically change a part's location in one simulation ?
ericsson.sunshine, There are lots of problems with your?20181130_subckt_stepping_ng_FFSD08120A_2p.zip example. You should start simple, then build up to more complex, not the other way around.? When you dive right in with many untried things, it's a good way to fail.? Get the simple case working first, before moving to more complex.? It's better to debug one thing at a time, instead of many at once. MODELs and SUBCKTs are never interchangeable.? It's one or the other. OnSemi's models are SUBCKTs, not MODELs.? Also, your diode symbol has Prefix = X, so it can ONLY use a SUBCKT.? Therefore, don't try the .MODEL statements. I do not believe that "AKO" can be used with SUBCKTs.? I think I have only seen it used with MODELs, not SUBCKTs, and I don't know how they could be used with subcircuits.? Also, every .SUBCKT line must be paired with an .ENDS line. There is no FFSD08120A_2p in OnSemi's library file. As I said earlier, STEPping SUBCKTs is potentially very dangerous.? It's not like STEPping MODELs.? Do you know that both subcircuits are fundamentally the same, inside?? Do you even know what's inside them?? Unless you are certain that both subcircuits have the same internal structure, I would advise against STEPping them. However, if you insist on taking that risk, here's one way to do it.? Encapsulate the subcircuits inside your own subcircuits named 1 and 2.? I will upload an example of this to the Temp folder. Here are more examples in the group's Files area for STEPping SUBCKTs: ? ? Files > Tut > Stepping to the max > stepping_subckt.asc ? ? Files > Tut > Stepping to the max > stepping_opamp_models1.asc ? ? Files > Tut > Stepping to the max > stepping_opamp_models1.asc ? ??Regards, Andy |
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Re: The simulation of the LTspice is blocked with sentence (if)
j.bernabe1 wrote: ? ? "I want to simulate a power supply with the statement (if) using the generator (bv.asy), and with the following condition : ? ? ?V=if(V(Vsense)>1.2,1,0)?? ? ? ?... ? ? ?The simulation do not work, is blocked,?It does not perform the transient analysis." I tried it, and it worked.? So, I guess you made a mistake.? Helmut's reply was correct, but I think you already did that. You also tried this: ? ? "V ={si(V(Vsense)>1.2,1,0)}" but that does not work because "si" is not a valid function name in LTspice.? It must be "if". ? ? "I would like to know the reason of the not simulation. ? ? ?You? know?the reasons why the simulation? does not work ?" None of us can say, because (1) we don't know what the error message was, and (2) we can't see your schematic.? The error message probably was not "blocked"; it probably was something else, and it said what was wrong. Please consider uploading your schematic to the "Temp" folder.? Also, please be more helpful by telling us the actual error message. Regards, Andy |
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The simulation of the LTspice is blocked with sentence (if)
Hi, friends.
I have a question, have a problem with the simulation about the sentence (if). I want to simulate a power supply with the statement (if) using the generator (bv.asy), and with the following condition : V=if(V(Vsense)>1.2,1,0)?? I have also tried with this : V ={si(V(Vsense)>1.2,1,0)} The simulation do not work, is blocked,?It does not perform the transient analysis.? I would like to know the reason of the not simulation. You? know?the reasons why the simulation? does not work ? AHh,?that generator is connected to the non-inverting input of the LTC6752 comparator. I wait can to have a good help, because for me, this simulation is very important, is for a innovative electronic design . Sorry by my bad level english. |
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Re: Is it possible to dynamically change a part's location in one simulation ?
Hi, Andy:
I'm sorry, this might be too short (not clear), I forgot to say the FPGA similarity, it simply read a setting file, which configures the cell setting (set or unset), so every different setting file mapping to different FPGA output, if mapping the requirement of this discussion about 'dynamical changing...', maybe the setting file of FPGA could be shorten to a table (from external file) content, or other else. Actually, that what I am thinking and ask for ideas, those hierarchy to implement it in LTspice, what's the better/best methods by combining those LTspice faetures (table, models, subckts, AKO alias, .STEP, etc) Thank you very much. Have a nice day! By the way, another question is, the mentioned 'batch' idea of "dynamically-changing-the-parts-location, etc." before, could you shed some possible ways , if I hope to simplify those configurations of 'topologies' in a simplified 'table' which contain the info of what's set & what's unset, the hierarchy of those .model , subckt in LTspice , what's the best looking can it be as clear as possible for easy-reading. |
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Re: Is it possible to dynamically change a part's location in one simulation ?
Hi, Andy:
Thank you, I have ran successfully the stepping .model simulations. May I ask , do you have any idea of example of describing stepping subckt (what you have mentioned) , because I can't get it done. I have uploaded a file named '20181130_subckt_stepping_ng_FFSD08120A_2p.zip' at the temp folder. I hae tried two syntax , but it shows 'unknown subcircuit call'': 1). .subckt 1 ako:FFSD08120A_2p ;the existing FFSD08120A_2p subckt now also known as "1" .subckt 2 ako:FFSD10120A_2p ;the existing FFSD10120A_2p subckt now also known as "2" 2). .model 1 ako:FFSD08120A_2p ;the existing FFSD08120A_2p subckt now also known as "1" .model 2 ako:FFSD10120A_2p ;the existing FFSD10120A_2p subckt now also known as "2" By the way, another question is, the mentioned 'batch' idea of "dynamically-changing-the-parts-location, etc." before, could you shed some possible ways , if I hope to simplify those configurations of 'topologies' in a simplified 'table' which contain the info of what's set & what's unset, the hierarchy of those .model , subckt in LTspice , what's the best looking can it be as clear as possible for easy-reading. Thank you very much. Have a nice day! ---In LTspice@..., <ai.egrps@...> wrote : LTspice has a limited ability to .STEP through different models for the same part.? But it's somewhat risky. You can use .STEP to change a transistor's (or diode's) .MODEL, if you define those .MODELs with numeric names: ? ? .MODEL 1 NPN (...) ? ? .MODEL 2 NPN (...) and so on. The same thing SOMETIMES works for subcircuits too, if you're careful, using numeric subcircuit names.? However, if the subcircuits differ in a substantial way, then it fails, without warning.? I believe the problem is that LTspice reserves memory for the network's matrix once, and uses the same memory space for all .STEPped runs.? So if the subcircuits use a different amount of memory, or structure it differently, LTspice may end up walking all over its own memory and it corrupts the data. I think it is much safer to either run consecutive simulations (each with their own schematic or netlist), or combine circuits into the same schematic.? You make it sound like combining circuits is very inefficient.? Often it is not.? Don't dismiss it if it may work. Regards, Andy |
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Re: Is it possible to dynamically change a part's location in one simulation ?
ericsson.sunshine wrote: ? ? "About the efficieny, I didn't mean affecting the application of the simulation for, I simply meant the 'spent time' of accomplishing the simulation(s)." That is what I meant too. Sometimes combining a few circuits in the same LTspice simulations makes it very slow, but sometime it doesn't.? If 3 circuits in the same schematic page make LTspice run 3 times slower than each one alone, then it is not worse than having 3 separate schematics and running them one-by-one. Andy |
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Re: Is it possible to dynamically change a part's location in one simulation ?
ericsson.sunshine, don't be misled by what you saw in the Help, which (BY COINCIDENCE) has both ".STEP" and "NPN" in the same command line.? That one is a very special case of the .STEP command. For more about stepping .MODELs themselves, see this: ? ? but even that might be confusing because it combines stepping a model, with the "AKO" syntax. ?Here are examples of stepping a model, without AKO: ? ? .model 2222 NPN (IS=1E-14 VAF=100 BF=200 IKF=0.3 XTB=1.5 BR=3 ...) ? ? .model 3904 NPN (IS=1E-14 VAF=100 Bf=300 IKF=0.4 XTB=1.5 BR=4 ...) ? ? .model ?849 NPN (IS=5.8591E-13 NF=0.9919 BF=230 IKF=18 VAF=90 ...) ? ? .model 1048 NPN (Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=495 Ne=1.28 ...) ? ? .step param BJT?list 2222 3904 849 1048 or this: ? ? .model 1 NMOS (Vto=0.8 Kp=48u Gamma=0.30 Phi=0.55 Lambda=0 Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0) ? ? .model 2 NMOS (LEVEL=2 L=1u W=1u VTO=-1.44 KP=8.64E-6 NSUB=1E17 TOX=20n) ? ? .model 3 NMOS (KP=90u VT0=0.7 LAMBDA=0.01) ? ? .model 4 NMOS (VTO=0.4 KP=432E-6 GAMMA=0.2 PHI=.88) ? ? .step param MyMOS?list 1 2 3 4 Then you would have an NPN transistor symbol with the name changed to {BJT}, or an NMOS transistor symbol with the name changed to {myMOS}.? When the simulation runs, LTspice replaces that name with the number(s) from the .STEP command, which makes LTspice choose the appropriate .MODEL?for that transistor. Because LTspice already has several .MODEL statements for transistors in its library, and more that can be downloaded from the Internet, it is convenient to not have to modify them so that their model names are strictly numeric.? That's when the "AKO" syntax comes in handy.? But it's not really necessary. Regards, Andy On Thu, Nov 29, 2018 at 8:21 PM ericsson.sunshine@... [LTspice] <LTspice@...> wrote: > > > > Hi, Andy: > > Thank you for the answering. > > About the .STEP & .MODEL 1 NPN(...) , may I ask if there is any example already ? I could understand the '.MODEL1 NPN(...)' syntax in standard.bjt, but I don't understand how to parse it in .STEP, in the help, I saw: > > Example: .step NPN 2N2222(VAF) 50 100 25 > > Step NPN model parameter VAF from 50 to 100 in steps of 25. > > > But I think this only change the value of VAF , one attribute of 2N2222, how to change the whole model configuration ? The syntax for '.STEP xxx ...' is ? > > I think maybe, could defaultly put many components similar to FPGA cells, then configure them set or unset, by normal or high/low impedance, etc. (Still ideas). > > About the efficieny, I didn't mean affecting the application of the simulation for, I simply meant the 'spent time' of accomplishing the simulation(s). Therefore, it should represent the efficiency of user's working. Sorry for the unclear description. > > Have a nice day! > > > ---In LTspice@..., wrote : > > LTspice has a limited ability to .STEP through different models for the same part.? But it's somewhat risky. > > You can use .STEP to change a transistor's (or diode's) .MODEL, if you define those .MODELs with numeric names: > ? ? .MODEL 1 NPN (...) > ? ? .MODEL 2 NPN (...) > and so on. > > The same thing SOMETIMES works for subcircuits too, if you're careful, using numeric subcircuit names.? However, if the subcircuits differ in a substantial way, then it fails, without warning.? I believe the problem is that LTspice reserves memory for the network's matrix once, and uses the same memory space for all .STEPped runs.? So if the subcircuits use a different amount of memory, or structure it differently, LTspice may end up walking all over its own memory and it corrupts the data. > > I think it is much safer to either run consecutive simulations (each with their own schematic or netlist), or combine circuits into the same schematic.? You make it sound like combining circuits is very inefficient.? Often it is not.? Don't dismiss it if it may work. > > Regards, > Andy > > > > > |
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Re: Is it possible to dynamically change a part's location in one simulation ?
You know, if the computer resource is enough,?
I think maybe I could build the default of every possible architecture of the circuit topology in a single schematic, though at every single .STEP, mainly could only one main core (one topology in default setting many topologies schematic) in action (running simulation), but the others just only sink a little bit losses which could still sustain their presence in the schematic, while in the next .STEP, they will present their work, the meaning is they co-exist, and live, but need enough resource to sustain (wait) to the next .STEP, in the mean while, they have the same goal, to achieve the final application of the schematic for, server the customers. Does this sound reasonable ? Best regards. ---In LTspice@..., <ericsson.sunshine@...> wrote : Hi, Andy: Thank you for the answering. About the .STEP & .MODEL 1 NPN(...) , may I ask if there is any example already ? I could understand the '.MODEL1 NPN(...)' syntax in standard.bjt, but I don't understand how to parse it in .STEP, in the help, I saw: Example: .step NPN 2N2222(VAF) 50 100 25 Step NPN model parameter VAF from 50 to 100 in steps of 25. But I think this only change the value of VAF , one attribute of 2N2222, how to change the whole model configuration ? The syntax for '.STEP xxx ...' is ? I think maybe, could defaultly put many components similar to FPGA cells, then configure them set or unset, by normal or high/low impedance, etc. (Still ideas). About the efficieny, I didn't mean affecting the application of the simulation for, I simply meant the 'spent time' of accomplishing the simulation(s). Therefore, it should represent the efficiency of user's working. Sorry for the unclear description. Have a nice day! ---In LTspice@..., <ai.egrps@...> wrote : LTspice has a limited ability to .STEP through different models for the same part.? But it's somewhat risky. You can use .STEP to change a transistor's (or diode's) .MODEL, if you define those .MODELs with numeric names: ? ? .MODEL 1 NPN (...) ? ? .MODEL 2 NPN (...) and so on. The same thing SOMETIMES works for subcircuits too, if you're careful, using numeric subcircuit names.? However, if the subcircuits differ in a substantial way, then it fails, without warning.? I believe the problem is that LTspice reserves memory for the network's matrix once, and uses the same memory space for all .STEPped runs.? So if the subcircuits use a different amount of memory, or structure it differently, LTspice may end up walking all over its own memory and it corrupts the data. I think it is much safer to either run consecutive simulations (each with their own schematic or netlist), or combine circuits into the same schematic.? You make it sound like combining circuits is very inefficient.? Often it is not.? Don't dismiss it if it may work. Regards, Andy |
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Re: Is it possible to dynamically change a part's location in one simulation ?
Hi, Andy:
Thank you for the answering. About the .STEP & .MODEL 1 NPN(...) , may I ask if there is any example already ? I could understand the '.MODEL1 NPN(...)' syntax in standard.bjt, but I don't understand how to parse it in .STEP, in the help, I saw: Example: .step NPN 2N2222(VAF) 50 100 25 Step NPN model parameter VAF from 50 to 100 in steps of 25. But I think this only change the value of VAF , one attribute of 2N2222, how to change the whole model configuration ? The syntax for '.STEP xxx ...' is ? I think maybe, could defaultly put many components similar to FPGA cells, then configure them set or unset, by normal or high/low impedance, etc. (Still ideas). About the efficieny, I didn't mean affecting the application of the simulation for, I simply meant the 'spent time' of accomplishing the simulation(s). Therefore, it should represent the efficiency of user's working. Sorry for the unclear description. Have a nice day! ---In LTspice@..., <ai.egrps@...> wrote : LTspice has a limited ability to .STEP through different models for the same part.? But it's somewhat risky. You can use .STEP to change a transistor's (or diode's) .MODEL, if you define those .MODELs with numeric names: ? ? .MODEL 1 NPN (...) ? ? .MODEL 2 NPN (...) and so on. The same thing SOMETIMES works for subcircuits too, if you're careful, using numeric subcircuit names.? However, if the subcircuits differ in a substantial way, then it fails, without warning.? I believe the problem is that LTspice reserves memory for the network's matrix once, and uses the same memory space for all .STEPped runs.? So if the subcircuits use a different amount of memory, or structure it differently, LTspice may end up walking all over its own memory and it corrupts the data. I think it is much safer to either run consecutive simulations (each with their own schematic or netlist), or combine circuits into the same schematic.? You make it sound like combining circuits is very inefficient.? Often it is not.? Don't dismiss it if it may work. Regards, Andy |
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