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Hello there group members, I'm trying to simulate a Sallen Key filter with a cutoff frequency of around 40kHz using a unipolar 5V source (See TEMP section). The initial operating point solution does

In order to copy a schematic or part of one to another schematic, you have to have both schematics open in the same instance of LTspice. Open them both before you try to copy. Best wishes John

I thought it would work to select/duplicate a portion of a schematic and drag it into a new window? But for the moment I can't find the protocol how to perform this. With a copied circuit hanging on

Thanks, nice trick. — Christoph

I name all nodes that might be "interesting" so I know where everything is. Donald. -- *Plain Text* email -- it's an accessibility issue () no proprietary attachments; no html mail /\

Hello Christoph, There is no cross probing available, but there is a workaround. Click the "search"-icon on the toolbar and enter the netname. Then the net will be highlighted. Best regards, Helmut

To find a signal name in the schematics, is it possible to highlight this signale, e.g. from the plot view? I have a lot of signal names but can't find them quicklx in the circuit drawing. --

Hello analogspiceman What was his response? I'm also curious because, by chance, I saw this topic come up on electronics.stackexchange a few days ago. -- Vlad ______________________

I recently asked Mike if would be possible to add a new feature to .savebias and .loadbias invoked by the keyword “eachstep” whereby in a stepped simulation, each succeeding step would load the

thanks all

wgrandner wrote, "What does Heightened Def Con mean ?" It means LTspice is having some trouble, but hasn't given up yet. In your case, it may mean there is something in your circuits that is making

When I run simulations, I get a messages in the Spice error log stating Heightened Def Con from 0.00011015 to 0.00011015 In most of my simulations I get over 100,000 messages, where the number is

ericsson.sunshine, There are lots of problems with your 20181130_subckt_stepping_ng_FFSD08120A_2p.zip example. You should start simple, then build up to more complex, not the other way around. When

j.bernabe1 wrote: "I want to simulate a power supply with the statement (if) using the generator (bv.asy), and with the following condition : V=if(V(Vsense)>1.2,1,0) ... The simulation do not work, is

Hello, A standard V-source in SPICE cannot be a behavioral source. You have to use a Bv-source. Add a "bv" and change V=F(...) to the formula below. V=if(V(Vsense)>1.2,1,0) Best regards, Helmut

Hi, friends. I have a question, have a problem with the simulation about the sentence (if). I want to simulate a power supply with the statement (if) using the generator (bv.asy), and with the

Hi, Andy: I'm sorry, this might be too short (not clear), I forgot to say the FPGA similarity, it simply read a setting file, which configures the cell setting (set or unset), so every different

Hi, Andy: Thank you, I have ran successfully the stepping .model simulations. May I ask , do you have any idea of example of describing stepping subckt (what you have mentioned) , because I can't get

Update: The Nov. 29 2018 release fixes this problem. Thanks!

re: "Does this sound reasonable ?" I'm sorry, but I don't understand what you wrote (in the paragraph before the question). Andy