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Re: Li-ion BAttery models
The writings(code) on the circuit are clumsy and i could not infer anything ......can u plz mail me only the circuit with values separately? On Friday, May 30, 2014 12:08 AM, "thutches@... [LTspice]" wrote:
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Lohith, The circuit I uploaded contains a Battery model that can be used to simulate a Li-Ion battery. Tim
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Re: How can I make my simulation oscillate like my poorly designed PC board does?
Thanks for all of the help and suggestions!? I had the feedback going to the drain, instead of 5nH away from the drain.? I started noticing a little wiggle, and then changed parts until I was getting results similar to my bad PC board.? I noticed that the type of FET (model) made a big difference in the sensitivity to oscillation.? Once I got the "good" oscillations, I found that a series damping resistor could eliminate the effect.? In addition to lower inductance routing, the new layout will have the extra resistor to eliminate the possibility of this oscillation. I've uploaded a file demonstrating the cause and cure of the oscillation (Oscillating Miller FETs 03.asc).? Thanks for the education! Carl |
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Re: How can I make my simulation oscillate like my poorly designed PC board does?
Carl wrote:
? ?"I've uploaded a version of the file "Oscillating Miller FETs 02.asc" to the files/temp directory.? This file has my interpretation of your suggestions ..."
Maybe you forgot the 5nH to be added to the drain leads. ?You are still taking both the Miller cap feedback and the output from the on-die end rather than the external end of that 5nH lead inductance.
But I couldn't make it fully oscillate either. ?I got a tiny bit of ~160 MHz appearing at the gate input side of the FET in the slower circuit, but did not see the same at its output. You mentioned adding a 47 ohm resistor in series with the gate drive. ?What exactly was your gate drive? ?Did the source have its own source impedance too? ?(Again, not that it makes it oscillate; it's just an observation/question.) Regards, Andy |
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Re: differimproved
Marcel wrote:
? ?"I uploaded differimproved.zip in /temp."
You forgot to include the models for the output transistors, QBD139 and QBD140.
It's generally not a good idea to refer to unnamed nodes (N007 and N008) in the plots, when you save the .PLT file for later use. ?I might not get the same nodes when I run it on my computer (though I probably will); and if I change anything in the schematic, those node names change.
How are you measuring the THD? ?This is a transient analysis, which makes me think you will do an FFT. ?If so, it is essential that you turn off waveform compression:
.options plotwinsize=0 This is quite possibly why your LTspice simulation has the distortion it has. ?Look at the bottom of the Help page for Waveform Viewer > Waveform Arithmetic, and note how the simulation there uses both plotwinsize=0 and numdgt=15, to get the best waveform accuracy for the FFT.
You also ought to have many waveform points per sine wave. ?Your simulation calls for a maximum timestep of 100us, which means only 10 samples per cycle. ?It might work OK with that, but I'd feel better with more samples per period.
Running your simulation with other output transistors, the amplifier does not seem to be very symmetrical and it is not biased right. ?Why does C5 have an initial condition of 7.5V ? ?I think that's wrong, given that the supply voltage is 7.5V and that C5's voltage ultimately needs to reach ~0V.
Also, why use UIC? ?You have this great simulator which can figure out the initial operating point for you; why not use it? Regards, Andy |
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Re: How can I make my simulation oscillate like my poorly designed PC board does?
Can you upload a picture of the circuit so we can see what the layout parasitics should be like?
I've looked at BJT modeling a lot, and I can say it is very difficult to even get enough measurements to make the RF behavior right. Few datasheets have enough information. If you want to copy oscillation in real-life, this is critical. I imagine FETs aren't much different. At a few hundred MHz it's easily possible your model isn't accurate at all. Most models do a very poor job, though I can't speak directly to the quality of this specific model. I notice it is very short with few parameters however - not a good sign. |
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Using parameters and functions when defining a plot
Is it possible to scale a trace by a parameter defined on the schematic? Like:? .param maxvolts=122, and then plot V(c1)/maxvolts . Such a thing works when adding the parameter statement to the plotdef file in the scad3.exe directory, but that is not very?handy because these constants aren't universal?(in the project directory would be better already). Likewise, I sometimes scale a plot by a computed number, say the max value of the current when doing an FFT. It would be nice if these constants could be evaluated before a plot is made ( V(c1)/max(V(c1)) or something like that? -marcel |
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differimproved
I uploaded differimproved.zip in /temp. It is a simulation of a simple audio amplifier. Somewhat to my surprise my modifications didn't lead to the expected decrease in THD. Checks with another simulator (NGSPICE) shows that the THD does decrease. It also showed that LTSpice is about 3 to 6 times slower than NGSPICE for this problem. Of course this can't be true :-) Does?anybody spot the problem?on this schematic? There must be "something one is not supposed to do" on it. -marcel |
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Re: How can I make my simulation oscillate like my poorly designed PC board does?
The Miller cap is not added to stop the oscillation, but to slow the switching edges.? You can see the edge slow-down effect in the uploaded file (Files/Temp folder).? The simulation has a pair of the circuits, one with, and one without the 300pF cap that performs the slow-down.? Without the slow-down, there is a 30MHz spike in the PCB emissions scan, related to the edge rate of the switching waveform.? By adding the cap, along with a 47 ohm resistor in series with my gate drive, the slower edge rate lowers the emissions at that frequency by about 10dB, which is my goal.? Of course, this allows for any high-Q circuit strays to try to oscillate, which is what I'm trying to simulate.
I've tried your suggestions, but the simulation still shows no sign of oscillating.??Am I still doing something wrong with my quest for oscillation? I've uploaded a version of the file "Oscillating Miller FETs 02.asc" to the files/temp directory.? This file has my interpretation of your suggestions, but I still can't make it oscillate.? I've tried a variety of component values and several different FETs, looking for a hint of oscillation.? Can somebody make it oscillate for me? thanks, Carl
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Re: In situ changing of a MOSFET Rdson in the subcircuit
¿ªÔÆÌåÓýHello Waynel,please have a look to these Application Notes: In : (a very interesting collection) ->Discretes ->FETs (97) ->Mosfets (86) ->AN-7532 ->AN-7533 ->AN-7534 There are a lot of MOSFET and IGBT models at the homepage of this company which have the electrical and thermal function: There are also such models available from other companies. Please give me an information if such models works with LTspice. Note: Mr. Alain Laprade which was one of the authors of these FAIRCHILDSEMI application notes is currently "Senior Applications Engineer at ON Semiconductor" Best regards Bernhard Valouch Germany -- Bernhard Valouch |
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Re: Is the Group down?
Ian Field
Yahoo is being its normal self - as usual!!! I signed up for LTspice posts, but users of other groups that didn't are now complaining about an inbox full of LTspice messages. Yahoo needs a web designer that wasn't dropped on their head when they were little. On Thursday, 29 May 2014, 20:56, "Dan Andersson dan@... [LTspice]" wrote:
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Re: Is the Group down?
Yahoo's gone mental. Other groups are affected to.
//Dan, M0DFI On Thu, 29 May 2014 22:12:32 +0300 "Vlad imbvlad@... [LTspice]" <LTspice@...> wrote: Hello |
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Re: Is the Group down?
Same for me. I see some note while waiting about "waiting for proxy." --s.a.hill (new to group) On Thu, May 29, 2014 at 3:12 PM, Vlad imbvlad@... [LTspice] <LTspice@...> wrote:
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Is the Group down?
Hello
I keep getting errors whenever I try to access the web page of the Group, no matter if it's the files or the conversations, but I seem to be able to post replies from within GMail. Is this a general (hopefully temporary) flaw? Vlad ______________________ ltspicegoodies.ltwiki.org -- holding, among others: a universal analog/digital filter, block-level models for power electronics (and not only), math blocks with a more stream-lined approach, some digital ADC, DAC, (synchronous-)counter, JKflop, etc. |
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Re: Clipping a Universal op-amp
On a second thought, the "sw" only might do (it has "vt" and "vh"),
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but if an additional delay is needed (to avoid "time step too small: errors), the comparator will come in handy. Vlad ______________________ ltspicegoodies.ltwiki.org -- holding, among others: a universal analog/digital filter, block-level models for power electronics (and not only), math blocks with a more stream-lined approach, some digital ADC, DAC, (synchronous-)counter, JKflop, etc. I don't really understand your purpose but, given what you have said:OK: Now can I rig a feedback which essentially lies dormant until theyou could make use of a comparator (use the Schmitt A-device with "vt=50m |
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Re: Li-ion BAttery models
Thx Woody
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Re: Clipping a Universal op-amp
I don't really understand your purpose but, given what you have said: > OK: Now can I rig a feedback which essentially lies dormant until the > error voltage exceeds maybe 50mV, then jumps in to force balance?
you could make use of a comparator (use the Schmitt A-device with "vt=50m vh=0") and a VCVS (element "sw") with proper Ron/Roff. I'll just leave the "how" and "why" for yourself. Vlad ______________________ -- holding, among others: a universal analog/digital filter, block-level models for power electronics (and not only), math blocks with a more stream-lined approach, some digital ADC, DAC, (synchronous-)counter, JKflop, etc. |
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Re: Clipping a Universal op-amp
Well, suppose you have a gain 2 non-inverting setup. Vin+ > Vdd/2 means the op-amp cannot actually make the summing node Vin- anything like Vin+.
So Vdd=5, Vin+=5, Vin- = B.rail = 2.5: error is +2.5 - not a "working/normal" error voltage but an ERROR voltage (big time). So the output hits the rails. As Vin + gets higher, the error voltage Vin+ - Vin - rises from a normal "enough to drive the loop via AB" to something crazy lit 1, 2 or more volts. OK: Now can I rig a feedback which essentially lies dormant until the error voltage exceeds maybe 50mV, then jumps in to force balance? Yes - the output will not then be 'correct'. But it would be wrong anyway, and I at least the output is not at the rail. |
thutches