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Is there any way to limit the number of voltages and
currents that are saved during a transient analysis?
[...]

Use the .save command to list those nodes and voltages
that you wish. If there is no .save command, then it
saves the defaults, which you can set in
Tools=>Control
Panel=>Save Defaults.(That's where you tell it to save
subcircuit nodes and device currents if you wish).

Also of interest might be the special .save keyword
of "dialogbox". For example, the syntax

".save V(in) V(out) dialogbox"

will throw up a dialog box at the start of simulation
of nodes and currents to save. V(in) and V(out) will
be selected and you can select other quantities by
clicking on the nodes/devices in the schematic.

--Mike

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Is there any way to limit the number of voltages and currents that
are saved during a transient analysis? Over the weekend I ran a
simulation of a poly-phase voltage regulator. The resulting data
file was nearly 5G! It took about 20 minutes this morning just to
load up 7 or 8 traces to view. I've noticed that the time to load a
trace grows with the number of nodes, not just the simulation period,
so I'm thinking that I could save a lot of time if I could be
selective about what data I save.

Also, is there a way to selectively export plot data? It would be
really nice to be able to bring particular traces into Mathcad, for
example, for more detailed analysis. It would also be very
beneficial to be able to e-mail data to plot a few traces.

Thanks,
John

--- In LTspice@..., Panama Mike <panamatex@y...> wrote:

Dale wrote:

Mike, this sounds like something I'd like to
dissuade you from.

Helmult wrote:
I fully agree with you. The biggest advantage
of all the opamp models
[...]
The provided SPICE models should be also optimized
for good convergence in the simulation. If a model
doesn't provide some features like noise modeling
(.AC), it should behave more like an ideal
component in such a type of simulation.

The problem is that the PSpice models often don't
converge very well and don't model noise correctly.
That has nothing to do with Linear's opamp models,
it's common to most Boyle style models.

Hello Mike,
I have never said here that it is specific for LT models. My
statement has been a general one for all vendor's models.
If it is true that the Boyle model is so weak, why not starting with
another SPICE model? I am shure that LT has the right people(you for
example) to make excellent models.

They don't
converge well in PSpice either. It's just a really
lame modeling methodology. Sometimes I honestly
get the impression that SPICE macromodeling
engineers tweak a model until it doesn't run anymore
and pronounce it done at that point, blaming any
convergence problems are due to the simulator.

I have experimented with my own generic opamp model and indeed it
converges very different depending on the choosen circuit.

LTSPICE has been greatly improved over the last year regarding
convergence problems. Most of the problems seem to be history.

Of course the advantage of being able to run
them in PSpice is important.

There are even more SPICE simulators around. Some of them are
specific SPICE simulators like ICAP and others are part of PCB-CAD
packages. All these users need/want SPICE models of LT opamps.
Finally I hope that LT always provide opamp models for the whole
SPICE "family" too.

Best Regards
Helmut

Dale wrote:

Mike, this sounds like something I'd like to
dissuade you from.

Helmult wrote:
I fully agree with you. The biggest advantage
of all the opamp models
[...]
The provided SPICE models should be also optimized
for good convergence in the simulation. If a model
doesn't provide some features like noise modeling
(.AC), it should behave more like an ideal
component in such a type of simulation.

The problem is that the PSpice models often don't
converge very well and don't model noise correctly.
That has nothing to do with Linear's opamp models,
it's common to most Boyle style models. They don't
converge well in PSpice either. It's just a really
lame modeling methodology. Sometimes I honestly
get the impression that SPICE macromodeling
engineers tweak a model until it doesn't run anymore
and pronounce it done at that point, blaming any
convergence problems are due to the simulator.

Essentially all customer-reported SwCADIII
convergence problems reported deal with using
these opamp models. But inside the mixed-mode
simulator in LTspice is the ability to model
an opamp model like I described. Few convergence
problems, one or two internal nodes, good noise
modeling and almost no load on the simulation
run time. The technology already exists in
LTspice and is used in the SMPS products' error
amps.

Another problem I have is there's some newer
Linear opamps that don't have any SPICE models.
If I go to this new method, then I can make a
model in less than an hour that will be more
accurate than the former PSpice models. It's
much cheaper and it's hard to justify these
expensive PSpice models that don't work well.
Of course the advantage of being able to run
them in PSpice is important.

--Mike

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--- In LTspice@..., "Dale" <dchishol@c...> wrote:

--- In LTspice@..., Message 141, Panama Mike
<panamatex@y...> wrote:
< snip >

BTW, I'm thinking of introducing opamp models that
use a different modeling methodology, similar to
that used for LTspice's SMPS products. The result
would be computationally extremely lightweight and
robust models that model noise too(these PSpice-
style opamp models almost never get the noise
modeled). However, the opamps models would not
run in other SPICE simulators and non-LT opamp
models wouldn't be available. Would you folks be
interested in something like that?

--Mike

Mike, this sounds like something I'd like to dissuade you from.

Part of the strength of the SPICE methodology is that the models are
transmitted as "open source", simple text files. The most

significant

advantage is that we Mere Mortals can easily extend, improve,

correct,

or modify models as needed.

Hello Dale,
I fully agree with you. The biggest advantage of all the opamp models
from different vendors is that they follow the general accepted SPICE
syntax. This standard has been the base for the success of SPICE over
the last thirty years. This is at least true for most of the analog
parts like diodes, transistors, passive components and the opamps.

It may be different for SMPS, because they are much more mixed signal
devices. Here we have a lack of standard for digital parts and also a
missing standard for behavioral language syntax. One more reason is
the needed compuational speed of SMPS models for effective usage. I
believe it is ok to have special models for the SMPS, because they
are developed independently of the other anaolg/digital circuits of a
design.

Hello Mike,
I recommend to keep the "easier" parts like opamps compatible with
standard (P)SPICE, because many of LT customers use other SPICE
simulators for different reasons.
The provided SPICE models should be also optimized for good
convergence in the simulation. If a model doesn't provide some
features like noise modeling (.AC), it should behave more like an
ideal component in such a type of simulation.

Best Rgeards
Helmut

--- In LTspice@..., Message 141, Panama Mike
<panamatex@y...> wrote:
< snip >

BTW, I'm thinking of introducing opamp models that
use a different modeling methodology, similar to
that used for LTspice's SMPS products. The result
would be computationally extremely lightweight and
robust models that model noise too(these PSpice-
style opamp models almost never get the noise
modeled). However, the opamps models would not
run in other SPICE simulators and non-LT opamp
models wouldn't be available. Would you folks be
interested in something like that?

--Mike

Mike, this sounds like something I'd like to dissuade you from.

Part of the strength of the SPICE methodology is that the models are
transmitted as "open source", simple text files. The most significant
advantage is that we Mere Mortals can easily extend, improve, correct,
or modify models as needed.

The parent thread for this posting is a good example. Because almost
everything about the model was in plain view, several minds were
independently analyzing the problem and solving it. I cannot imagine
the problem being resolved nearly as quickly if the model's topology
and parameter values had been locked-up in a proprietary format
readable only by a few people.

The SPICE methodology permits individuals to customize models as
needed. If, for instance, noise is a critical performance
characteristic the necessary elements can be readily included to model
it. Otherwise they may be omitted. Similarly, a small-signal stage
where output limiting is not a concern can get by with a simplified
output circuit in the model.

Along the same line it is relatively easy to adjust model parameters
to fit particular situations. The model can be customized to reflect
the device's behavior at, say, a temperature extreme. Or an engineer
can investigate the implications of using a device whose performance
parameters (like offset voltage or slew rate) are near the data sheet
limits. Likewise the need for parts specially selected for certain
characteristics (such as low offset current) can be evaluated.

Finally the current SPICE modeling methodology allows engineers to
quickly create workable models for new or alternative components.

I hope that whatever modeling methodology you choose will retain these
features.

Dale

Quite apart from LTSpice, please accept a moral and ethical
commendation. By living in another culture & learning its language
you are promoting international understanding and respect for all
persons. This is unusual even among educated professionals. When I
was rushed to Mexico City after the earthquake, I learned that one of
my co-workers believed ANYBODY could understand English if only it was
spoken loudly and clearly enough.

An old joke asks, "If somebody who speaks 3 languages is trilingual
and somebody who speaks 2 languages is bilingual, what term describes
somebody who speaks but one language?" The answer, of course, is
"American". This situation is a symptom of a larger arrogance and
self-centeredness which we never intended to cultivate and are
certainly not proud of, but which often limits our ability to accept
others as truly human and our equals. (Yes, I include myself in that
indictment: with the minimal Spanish I learned in High School I could
bumble through ordering from a menu, and possibly even ask for
directions, but writing a coherent paragraph, reading a newspaper or
even normal conversation are beyond me. )

Again, thanks for doing your part. I hope nobody recognizes that I
carry a Scottish name and expects me to reply in Gaelic . . .

--- In LTspice@..., Arnold Esper <arnold.esper@n...>
wrote:

Hallo Helmut and Mike Engelhardt,

thanks for finding and solving the +problem. My (LTspice-)World

doesn't seem to

collapse in the near future any more.

Hello Arnold and all LTSPICE users.
I have uploaded an example how your netlist based circuit can be
converted to a LTSPICE schematic and model file. It is hopefully all
explained in the comments in this schematic. All the necessary files
are in the files area of this group.

Files->Examples->Educational->From netlist to schematic

Have fun with it.

Thanks to Mike too for the correction of the '+' problem in the PWL
syntax.

Best Regards
Helmut

Arnold,

thanks for finding and solving the +problem.
My (LTspice-) World doesn't seem to collapse
in the near future any more.

Das freut mich. (English: Glad to hear it.)

Mr. Engelhardt, are you German? your Name is.

Nee, ich bin Amerikaner. Aber ich wohnte ein
Jahr in Mainz. Nicht bei der Army aber auf
der Uni. Das war in 1978. Man versteht meine
deutsch Errantnisse ist in der Zwichenseit
auseinander gefallen. Normaleweise versuche
ich nie auf deutsch zu schreiben.

(English: Nope, I'm American. But I lived
a year in Mainz, Germany. Not with the Army
but at the university. That was in 1978
and my German knowledge has fallen to pieces
in the meanwhile. Normally I avoid writing
in German Language.)

--Mike

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Hallo Helmut and Mike Engelhardt,

thanks for finding and solving the +problem. My (LTspice-)World doesn't seem to
collapse in the near future any more.

Mr. Engelhardt, are you German? your Name is.

Arnold

Helmut,

Would it be difficult to improve your
interpreter so that it correctly
accepts a '+' sign?

OK. What's happening is that the
'+' sign can be used to mean incremented
from the previous value. It's a PSpice
convention useful for time points as in

V2 1 0 PWL (0 0 +1m 1 +1m 0 +1m 1 +1m 0 +1m 1)

But I'll turn that off for the voltage
in a future version, since I don't think
it should do it for the voltage, just the
time.

The web has just been updated with a
version that doesn't interpret the '+'
sign as incremental from the previous
version for voltage but still does for
time.

Thanks for pointing out the problem.

--Mike

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Helmut,

Would it be difficult to improve your
interpreter so that it correctly
accepts a '+' sign?

OK. What's happening is that the
'+' sign can be used to mean incremented
from the previous value. It's a PSpice
convention useful for time points as in

V2 1 0 PWL (0 0 +1m 1 +1m 0 +1m 1 +1m 0 +1m 1)

But I'll turn that off for the voltage
in a future version, since I don't think
it should do it for the voltage, just the
time.

--Mike

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--- In LTspice@..., Arnold Esper <arnold.esper@n...>
wrote:

Guten Tag,
was sind das für Fehler in LT-Spice? Gerechnet mit LT-Spice und

Winspice3.

Hallo Arnold,
hier kann fast keiner deutsch, deshalb macht es wenig Sinn die Frage
zus?tzlich in deutsch zu stellen.

what sort of errors is this in LT-Spice? The Schematic is computed

with LT-Spice

and Winspice3 from Mike Smith.
V1 1 0 DC 0 AC 1 PWL(0 0V 1m 0V 5m -.6V 13m +.8V 17m 0V)

I had the same problem some times ago with a model I think. The
problem here is that LTSPICE cannot interpret the '+' sign of a
number. So simply remove the '+' at the beginning of any number.
V1 1 0 DC 0 AC 1 PWL(0 0V 1m 0V 5m -.6V 13m .8V 17m 0V)

WINSPICE and PSPICE! have no problem with the '+' sign.

I didn't find any control to max Time Steps in
the .trans analysis.
.TRAN 10u 20m

You have to give four parameters if you want specify a maximum time
step. The command line could look in your example like this one.
.TRAN 10u 20m 0 10u
The other chance is a .option command line.
.TRAN 20m
.OPTIONS maxstep=10u


Hello Mike,
would it be difficult to improve your interpreter so that it
correctly accepts a '+' sign?

Best Regards
Helmut

Guten Tag,
was sind das fr Fehler in LT-Spice? Gerechnet mit LT-Spice und Winspice3.

Hello,
what sort of errors is this in LT-Spice? The Schematic is computed with LT-Spice
and Winspice3 from Mike Smith. I didn't find any control to max Time Steps in
the .trans analysis.

Arnold


BEGRE00 Begrenzer mit Transistoren


* *
* B E G R E N Z E R T R A N S I S T O R E N 0 0 . C I R *
* *
* Begrenzer mit Transistoren und Dioden in der Gegenkopplung *
* Benutzter OPA: TL 051 *
* *
* 20.03.2003 Arnold Esper *
* *



* *
* Definition der Eingangsspannung VIN zwischen Knoten 1 und 0 mit AC *
* und Puls, AC mit 1VOLT, der Puls wird festgelegt durch : *
* *
* PULS(U1 U2 T_VERZOEGER T_ANSTIEG T_ABFALL T_WEITE T_PERIODE) *
* *
* U2_|_ _ ______________ ____ *
* | / &#92; / *
* | / &#92; / *
* | / &#92; / *
* U1-|-------- - - - - - ------------------------ *
* | *
* *
* T_VERZ |T_AN| T_WEITE |T_AB| *
* | T_PERIODE | *
* *

* *
* Definition einer Polygonquelle (piece-wise-linear) *
* *
* PULS(U1 U2 T_VERZOEGER T_ANSTIEG T_ABFALL T_WEITE T_PERIODE) *
* *
* _|_ ______________ *
* | / &#92; *
* | / &#92; *
* | / &#92; *
* u0-|------- - - - - - &#92;- - - - - - - - - - *
* | &#92; *
* | &#92;____________________________ *
* *
* | | | | | *
* t0 u0 t1 u1 t2 u2 t3 u3 t4 u4 *
* *


*V1 1 0 DC 0 AC 1 PULSE(0 .6 100u 1m 1m 1n 1s)

**** Polygon-Quelle **

V1 1 0 DC 0 AC 1 PWL(0 0 1m 0V 5m -.6V 13m +.8V 17m 0V)



R1 1 2 22K
R2 2 4 22K
R3 4 6 100K
R4 6 7 22K
D1 2 3 DI
D2 7 5 DI
Q1 3 6 7 BC550C
Q2 5 4 2 BC550C
*E0 7 0 0 2 100K
X1 0 2 60 70 7 TL051/TI

* Betriebsspannungen VP VN ***

VP 60 0 DC 15
VN 70 0 DC -15

**** Analysen ****

*.OPTIONS LIMPTS=10000
*.AC DEC 100 10 20000
*.PRINT AC VDB(7)
.TRAN 10u 20m
.PRINT TRAN V(7)
*.DC V1 -1 1 0.001
*.PRINT DC V(7)


.model DI D



.model BC550C NPN(Is=7.049f Xti=3 Eg=1.11 Vaf=23.89 Bf=493.2 Ise=99.2f
+ Ne=1.829 Ikf=.1542 Xtb=1.5 Br=2.886 Isc=7.371p
+ Nc=1.508 Ikr=5.426 Rc=1.175 Cjc=5.5p Mjc=.3132 Vjc=.4924 Fc=.5
+ Cje=11.5p Mje=.6558 Vje=.5 Tr=10n Tf=420.3p Itf=1.374 Xtf=39.42
+ Vtf=10)
* PHILIPS pid=bc549c case=TO92
* 91-07-31 dsq

*
* TL051 operational amplifier "macromodel" subcircuit
* created using Parts release 4.01 on 04/12/89 at 09:57
* (REV N/A)
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
.subckt TL051/TI 1 2 3 4 5
*
c1 11 12 3.988E-12
c2 6 7 15.00E-12
dc 5 53 dx
de 54 5 dx
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0 2.875E6 -3E6 3E6 3E6 -3E6
ga 6 0 11 12 292.2E-6
gcm 0 6 10 99 6.542E-9
iss 3 10 dc 300.0E-6
hlim 90 0 vlim 1K
j1 11 2 10 jx
j2 12 1 10 jx
r2 6 9 100.0E3
rd1 4 11 3.422E3
rd2 4 12 3.422E3
ro1 8 5 125
ro2 7 99 125
rp 3 4 11.11E3
rss 10 99 666.7E3
vb 9 0 dc 0
vc 3 53 dc 3
ve 54 4 dc 3.700
vlim 7 8 dc 0
vlp 91 0 dc 28
vln 0 92 dc 28
.model dx D(Is=800.0E-18)
.model jx PJF(Is=15.00E-12 Beta=185.2E-6 Vto=-1)
.ends

*

.END

Sean,

See the examples called wavein.asc and waveout.asc in
the "educational" folder and also see help files for .wave

It is very cool indeed!

Brad


--- In LTspice@..., "sean_schouten" <sean_schouten@y...>
wrote:

Hi!

I too am new to spice. I heard that you were supposed to export a
output-waveform to a Wav-file somehow. Can any-one tell me how?

Would be cool.

Cheers, Sean

Hi!

I too am new to spice. I heard that you were supposed to export a
output-waveform to a Wav-file somehow. Can any-one tell me how?

Would be cool.

Cheers, Sean

Steve,

[...]Is this a fluke? Is there any way to tell if
a model will predict noise performance in general
and 1/f noise in particular.

I'm afraid it probably was, unless noise was
dominated by the resistors of your circuit.
Noise doesn't appear to be modeled in the LT2018A
macro model.

I think the only opamp macro model that claims to
model noise is the LT1028N.

--Mike

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Thanks for the help on the Burr Brown amp.

Noise analysis is a nice feature of LTSpice. It's helpful to poke
around a circuit to see where noise is being generated. However, I
didn't put alot of credence into the actual predictions because of
potential limitations in the SPICE models.

Out of curosity, I compared the RMS noise in an actual circuit using
a couple of different op amps, including the LT2078A. I found that
the predicted noise was fairly close to the actual measured values.
The circuit is basically DC-coupled so 1/f noise is expected to be
significant.

Is this a fluke? Is there any way to tell if a model will predict
noise performance in general and 1/f noise in particular.

Steve H.

thanks Helmut, its running ok with models downloaded
from duncanamps.com
thanks a lot

guille

--- Helmut Sennewald <helmutsennewald@...>
wrote:

--- In LTspice@..., Bill Lewis
<wrljet@y...> wrote:

Please post any replies to this question to the

list.

I'm interested in vacuum tube modeling.

... and the obvious question: How do I relate the

previous info
with

the symbol.

Hello Bill,
you will find the symbol in the "misc" directory.
A short description follows:
1. Load the triode symbol into your schematic.
2. Replace the value 'triode' with the model name
used in the model
file. In this case it is '12AX7A'.
3. Put the model text into a file and store it in
your working
directory. That is the directory where your
schematic is.
4. Add the line .INCLUDE modelfilename in your
schematic.
That's it. This procedure will work for any kind of
part and you can
put as many models you want into one file.

It is important for any kind of symbol and model
that the pin order
is matching. Let's take a look to the triode symbol.
The provided
symbol has the pin order P(1), G(2), K(3). The model
text
uses .SUBCKT 12AX7A P G K . This means that P
is pin-1 G is pin-
2 and K is pin-3. We have luck, the pin order is the
same. If it is
different, then we could either change the order in
the model text or
in the symbol.

I have the ready to run example files attached.

By the way, the model isn't good at low Vpk
voltages. Take a look to
the Ip(Vgk, Vpk) plot to see what I mean.

Best Regards
Helmut




The model file: triode_12ax7a.sub
---------------------------------

* 12AX7A Triode PSpice Model 8/96, Rev. 1.0 (fp)
*
*

-------------------------------------------------------------------

* This model is provided "as is", with no warranty
of any kind,
* either expressed or implied, about the suitability
or fitness
* of this model for any particular purpose. Use of
this model
* shall be entirely at the user's own risk.
*
* For a discussion about vacuum tube modeling please
refer to:
* W. Marshall Leach, jr: "SPICE Models for
Vacuum-Tube Amplifiers";
* J. Audio Eng. Soc., Vol 43, No 3, March 1995.
*

-------------------------------------------------------------------

*
* This model is valid for the following tubes:
* 12AX7A/ECC83, 7025, 6EU7, 6681, 6AV6, 12DW7/7247
(Unit #1);
* at the following conditions:
* Plate voltage : 25..400V
* Grid voltage : 0..-3.5V
* Cathode current: 0..8mA
*
*
* Connections: Plate
* | Grid
* | | Cathode
* | | |
.SUBCKT 12AX7A P G K
E1 2 0 VALUE={45+V(P,K)+95.43*V(G,K)}
R1 2 0 1.0K
Gp P K
VALUE={1.147E-6*(PWR(V(2),1.5)+PWRS(V(2),1.5))/2}
Cgk G K 1.6P
Cgp G P 1.7P
Cpk P K 0.46P
.ENDS 12AX7A.SUBCKT 12AX7A P G K


The circuit file: triode_test.asc
---------------------------------

Version 4
SHEET 1 1104 692
WIRE 336 384 336 496
WIRE 368 288 368 224
WIRE 368 224 512 224
WIRE 512 336 512 224
WIRE 512 416 512 496
WIRE 512 496 336 496
WIRE 336 496 176 496
WIRE 176 496 176 448
WIRE 176 368 176 336
WIRE 176 336 320 336
WIRE 176 528 176 496
FLAG 176 528 0
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;Misc&#92;triode
368 336 R0
SYMATTR InstName U1
SYMATTR Value 12AX7A
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage 176
352 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL F:&#92;PROGRAMME&#92;LTC&#92;SWCADIII&#92;lib&#92;sym&#92;voltage 512
320 R0
SYMATTR InstName V2
SYMATTR Value 200V
TEXT 142 136 Left 0 !;dc V2 0 200 0.1 V1 -5 20 5
TEXT 136 176 Left 0 !.INCLUDE triode_12ax7a.sub
TEXT 592 136 Left 0 ;.dc V2 0 200 0.1 V1 -5 20 5
Ip(Vpk, Vgk)
TEXT 144 96 Left 0 !.dc V1 -5 20 0.1
TEXT 592 96 Left 0 ;.dc V1 -5 20 0.1
Ip(Vgk)

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Reinier,

Sounds interesting. Could you also
make a very simple opamp with the
output voltage limited to the
supply voltages? I sometimes get
Mega Volts in my circuit on 1 Volt
transients at the inputs.

Yes, the thing I have in mind would do
that. Below is a list prepared for
someone else who asked about this
offline:

I've in mind to model GBW, AOL, slew
limit, voltage and current noise and
corner frequencies for each(But not
model noise from input impedance
imbalance like from JFET input
products), dynamic current draw from
each rail, output voltage range,
output current limit, and input bias
current. That can all be modeled in
the modeling methodology used in the
SMPS products one one internal node.
Doing the real small signal transfer
above the dominate pole requires
more nodes. For example, the LT1028
can be done with two more nodes.
CMRR would not be particularly
modeled, but it would be non-zero.

--Mike

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