Re: Can't get to "Files" or "Photos" (was: LDMOS SPICE MODELS)
I am specifically looking for a PD55003 LDMOS model for a check
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I haven’t found anything close
Anyone?
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From: Matthew D'Entremont
Sent: Wednesday, April 16, 2025 1:01 PM
To: [email protected]
Subject: LDMOS SPICE MODELS
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I haven’t found the ability from the
/g/LTspice page to download the files from ??/g/LTspice/files/Temp.? Is this because of firefox or firewalls?
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Re: Can't get to "Files" or "Photos" (was: LDMOS SPICE MODELS)
There is no way we can tell what the problem
is, from the limited amount you tell us. What actually happens
when you try to download a file?
On 2025-04-16 17:00, Matthew
D'Entremont via groups.io wrote:
--
Best wishes John Woodgate RAYLEIGH Essex OOO-Own Opinions Only
If something is true: * as far as we know - it's science *for
certain - it's mathematics *unquestionably - it's religion
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Re: Mini Circuits PHA-13HLN Spice Model
The first step is always to ask the
manufacturer. But MiniCircuits are rarely used in large-signal
conditions.
On 2025-04-16 16:46, Evelyn Benabe via
groups.io wrote:
Is
there a non-linear model for Mini Circuits PHA-13HLN driver PA that
someone can share with me?
--
Best wishes John Woodgate RAYLEIGH Essex OOO-Own Opinions Only
If something is true: * as far as we know - it's science *for
certain - it's mathematics *unquestionably - it's religion
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Re: Mini Circuits PHA-13HLN Spice Model
On 16/04/2025 17:46, Evelyn Benabe via
groups.io wrote:
Is there a
non-linear model for Mini Circuits PHA-13HLN driver PA that someone
can share with me?
Highly unlikely. Did you ask Mini-circuits if they have one?
Mini-Circuits do provide S-Parameter data that you can use
(indirectly) with LTspice. That should be enough for you verify
small signal S11 and S22.
To use S-Parameters in LTspice, you need to first convert them to a
(linear) SPICE model with the S2SPICE utility program. You can
download that from the group's Files area: S2SPICE.
--
Regards,
Tony
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Can't get to "Files" or "Photos" (was: LDMOS SPICE MODELS)
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Mini Circuits PMA3-73-1W+ Spice Model
Is there a non-linear model for Mini Circuits PMA3-73-1W+?PA that someone can share with me?
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Mini Circuits PHA-13HLN Spice Model
Is there a non-linear model for Mini Circuits PHA-13HLN driver PA that someone can share with me?
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Re: creating gm/Id vs Id/W plot in ltspice
Try these lines in a pmos_vds_with_Width.plt
Plots Id(M1) and?d(Id(M1))/d(V(Vgs)) vs '?'
Donald.
[DC transfer characteristic]
{
?? Npanes: 1
?? {
????? traces: 2 {34603010,0,"Id(M1)"}
{524291,1,"d(Id(M1))/d(V(Vgs))"}
????? Parametric: "Id(M1)"
????? X: ('?',1,-8.8e-06,8e-07,-0)
????? Y[0]: ('?',1,-8.8e-06,8e-07,-0)
????? Y[1]: ('?',0,0,1e-06,1.4e-05)
????? Amps: ('?',0,0,1,-8e-06,8e-07,-0)
????? Units: "ohm-1" ('?',0,0,0,0,1e-06,1.3e-05)
????? Log: 0 0 0
?? }
}
On 4/16/25 00:44, john23 via groups.io
wrote:
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Hello Andy , both plots are dc sweep.
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Re: creating gm/Id vs Id/W plot in ltspice
Hello Andy , both plots are dc sweep.
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Re: creating gm/Id vs Id/W plot in ltspice
On Tue, Apr 15, 2025 at 02:19 PM, john23 wrote:
Hello Andy,I have two Y axes plots depending on the same X axes.
I want to create a plot of Y1 vs Y2.
Is it possible in LTspice?
As I wrote before, that depends.? Be more specific.
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What kind of simulation are you using?? Transient?? .DC?? .OP augmented with .STEP commands?
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What you are capable of plotting depends on the kind of simulation you used.
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The answers to many of your questions can be found by reading the Help that comes with LTspice.? We can recommend the things for you to try, but those things we recommend come from reading the Help, and trying it ourselves.? You should be capable of doing both yourself.
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Andy
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Re: creating gm/Id vs Id/W plot in ltspice
Open one plot pane, say the Y1 plot.
Right-click on the X-axis and look at 'Quantity plotted' in the
pane that opens. If it gives you a choice, pick Y2. It may not
give you a choice.
On 2025-04-15 19:19, john23 via
groups.io wrote:
Hello Andy,I have two Y axes plots depending on the same X
axes.
I want to create a plot of Y1 vs Y2.
Is it possible in LTspice?
Thanks.
--
Best wishes John Woodgate RAYLEIGH Essex OOO-Own Opinions Only
If something is true: * as far as we know - it's science *for
certain - it's mathematics *unquestionably - it's religion
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Re: creating gm/Id vs Id/W plot in ltspice
Hello Andy,I have two Y axes plots depending on the same X axes.
I want to create a plot of Y1 vs Y2.
Is it possible in LTspice?
Thanks.
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Re: creating gm/Id vs Id/W plot in ltspice
That depends.? Be more specific.
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Andy
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Re: when is a capacitor not (quite) a capacitor
Thanks Tony and Andy.? I'll try out GFARAD, sounds like it's the 'right' approach here.? I should study the wiki documentation for undocumented bits more closely.? Tomorrow I might try it on my home machine which is at 24.1.5.? What's interesting is the brittleness of the op point search in a circuit that contains only passives and amplifiers straight from ADI's install.? And Jerry I know schematics are helpful, but this is a bit proprietary and I would need to strip it down for upload here, which of course would probably eliminate the error... I did do a dump of problematic circuits to Mathias and Mike recently, I'm still bent out of shape by how easy it is to get LTspice to give an operating point with nodes that utterly fail KCL.? But one has to move on rather than b!tch about this generally fantastic free tool we all benefit from.? I just occasionally feel that the guys over there need a heads-up on things that aren't right.
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Re: creating gm/Id vs Id/W plot in ltspice
Hello, nasickly I have Y1 vs X? and Y2 vs X ,Is there a wat to combine them so I'll get a Y1 vs Y2 plot?
Thanks.
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Re: How to simulate the gate charge characteristic given in the datasheet of a mosfet?
On Fri, Apr 11, 2025 at 12:36 AM, Dennis wrote:
Ankit,
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I will try to address your questions.
Dear Dennis,
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A very good day to you.
Once again thank you so very much for answering all my questions. I am grateful to you, teacher. I apologise to you for replying with a delay.
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I will make use of the knowledge that you have shared with me. Soon I will upload some simulation files for review.
With Regards,
Ankit
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Re: when is a capacitor not (quite) a capacitor
On 15/04/2025 15:53, Andy I via
groups.io wrote:
On Tue, Apr 15, 2025 at 06:53 AM, Tony Casey wrote:
... Normally, unless otherwise specified, Rpar = ∞
in capacitors. This shouldn't be affected by the Gmin setting,
because Gmin is only placed across junctions. The option for
placing a conductance between each node is Gshunt. The default
for Gshunt is zero.
I think that is not quite true, but it is one of those
"surprises" that you may not have realized was there.
?
The LTwiki ()
says that there is a non-zero conductance across capacitors,
with the name GFARAD and value GFARAD*C, and that the default
GFARAD is 1e-12 Siement/farad which happens to equal GMIN.? The
Help page for .OPTIONS says the same.? In any event, you do have
the ability to controls the parallel conductance across your
capacitors:
?
? ? .OPTIONS GFARAD=0? ?; disables it
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The Help page says that the default GFARAD is 1e-12 and not
GMIN, but I wonder if its default value is really GMIN.? Note
that their units are not the same (one is Siemens and the other
is Siemens/farad) even though their values are the same.
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In addition, depending on how you connected your series LC
circuits, it's possible that you created floating nodes with no
DC path to ground.? For example, a series LC trap with one C is
probably OK but if it had two C's in series, it has a floating
node where the capacitors join, and LTspice "fixes" that
user-mistake by adding a GFLOAT conductance there.? That might
be in addition to the GFARAD*C conductance, but LTspice might
combine the two instead of giving you GMIN + GFARAD*C.
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GSHUNT is yet another thing, independent of all the above.
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If the log file pops ups every time, it means you
have warnings or errors. At least that is the case with
24.0.12 or 24.1.4. I haven't moved on yet.
Yes, and I don't think that can be disabled, except by
eliminating all errors and warnings.
I actually checked this before I wrote the message. I had a
schematic with just a default 100pF capacitor grounded at one end. I
set the? initial conditions as IC=10.
I ran:
.TRAN 0 6000 0 10m
..and the capacitor voltage at the end was still exactly 10V.
I got the same result in 17.1.15, 24.0.12 and 24.1.4.
From that I concluded there was no shunt resistor, unless explicitly
specified.
However, I just checked again, and adding numdgt=15 revealed ~62nV
discharge at 6ks. Then adding GFARAD=0 eliminated this discharge.
62nV is less than the single precision resolution at 10V, so it
would not normally be seen. With GFARAD=0 and with a 1e10T shunt
resistor, the discharge again was ~62nV.
So, I concede LTwiki and the Help are correct.
--
Regards,
Tony
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Re: when is a capacitor not (quite) a capacitor
Having posted a schematic (.asc) would probably have helped clearing the issue.
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Re: when is a capacitor not (quite) a capacitor
On Tue, Apr 15, 2025 at 06:53 AM, Tony Casey wrote:
... Normally, unless otherwise specified, Rpar = ∞ in capacitors. This shouldn't be affected by the Gmin setting, because Gmin is only placed across junctions. The option for placing a conductance between each node is Gshunt. The default for Gshunt is zero.
I think that is not quite true, but it is one of those "surprises" that you may not have realized was there.
?
The LTwiki () says that there is a non-zero conductance across capacitors, with the name GFARAD and value GFARAD*C, and that the default GFARAD is 1e-12 Siement/farad which happens to equal GMIN.? The Help page for .OPTIONS says the same.? In any event, you do have the ability to controls the parallel conductance across your capacitors:
?
? ? .OPTIONS GFARAD=0? ?; disables it
?
The Help page says that the default GFARAD is 1e-12 and not GMIN, but I wonder if its default value is really GMIN.? Note that their units are not the same (one is Siemens and the other is Siemens/farad) even though their values are the same.
?
In addition, depending on how you connected your series LC circuits, it's possible that you created floating nodes with no DC path to ground.? For example, a series LC trap with one C is probably OK but if it had two C's in series, it has a floating node where the capacitors join, and LTspice "fixes" that user-mistake by adding a GFLOAT conductance there.? That might be in addition to the GFARAD*C conductance, but LTspice might combine the two instead of giving you GMIN + GFARAD*C.
?
GSHUNT is yet another thing, independent of all the above.
?
If the log file pops ups every time, it means you have warnings or errors. At least that is the case with 24.0.12 or 24.1.4. I haven't moved on yet.
Yes, and I don't think that can be disabled, except by eliminating all errors and warnings.
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Andy
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Re: when is a capacitor not (quite) a capacitor
On 14/04/2025 23:03, Kendall
Castor-Perry via groups.io wrote:
Hi all - anyone seen or been bitten by this?? I'm working on
a middling-sized circuit, nothing fancy, all passives and
library ADI opamps, inamps and diff drivers.? Implementing a
little gain and (as you'd expect from me) some filtering
functions, including some series LC traps close to the inputs.?
It's one of those circuits that's on the edge of not finding a
DC op point (24.0.12 on this work machine, 24.1.x deffo not
ready for salaried work IMHO).? Series traps are from signal
nodes to ground.? So there's a capacitor on the branch between
that node and ground.? So in principle it cannot participate in
any DC op point calculations.? But...
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I get to the point where, slowly dropping down the inductor's
series resistor (most tests with internal but external seemed
similar), I would cross a threshold where it couldn't find an op
point.? Quite abruptly; for instance, Rs >=65 gave an op
point, Rs <=64 and lower did not. (alternate solver; didn't
test normal).? So, clearly, the NAM must have some DC path
across that cap.? Tried changing the Gmin setting from default
1E-12 to 1E-14.? Success!? Now all realistic configurations give
me an operating point.
?
This is something that could be fixed (hi @mstokowski and
@mborn) - by making sure that Gmin==0 across any capacitor
that's not otherwise set up to be different, _just_ during the
op point search.? Of course the DC solver needs to be robust to
hanging branches so there might need to be some topology
trim/prep, solving a slightly different matrix (the caps in
series case will probably be irritating).? So not trivial, just
simple... I have a sneaking feeling that some of my older op
point troubles could have been fixed up this way.
?
Another way of doing this would be to have a flag for a
capacitor to explicitly set Re (shunt admittance) to zero - but
that's much more work for the user.? Better for the code to do
it inherently (perhaps with a setting choice box).
?
Of course 24.1.5+ might already have fixed this, I can't try
that until at least this evening.
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Hope this is interesting and relevant -- K
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PS (1) how do you stop the .log file from popping up at the
end of each sim now, annoying and (2) where did the little
display of the key for which .step plotted to which color trace
go?
Something here is not quite right. Gmin is not a conductance across
all nodes. Normally, unless otherwise specified, Rpar = ∞ in
capacitors. This shouldn't be affected by the Gmin setting, because
Gmin is only placed across junctions. The option for placing a
conductance between each node is Gshunt. The default for Gshunt is
zero.
My guess is that the Gmin setting in you case is a red herring. It
may be affecting any models that have active devices, but presumably
your circuit has no convergence issues until the resonant traps are
added?
If the log file pops ups every time, it means you have warnings or
errors. At least that is the case with 24.0.12 or 24.1.4. I haven't
moved on yet.
--
Regards,
Tony
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John Woodgate
Tony Casey