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But, I want the characterization to be done in ltspice

This is really more of a design question than an LTspice question. You might have better chances of a useful answer by going to a forum focused on IC design.

How can I characterize gm vs W/L in ltspice. Can anyone provide the testbench explaining the proper steps?

Hi Tony, thank you! study in progress. Regards, Shengqiao

Hi Denys, Thank you! got that. Regards, Shengqiao Zheng

Thanks Tony, I need to spend some time to study this scenario of this new scheme.

Try this page: https://www.onsemi.com/products/power-management/ac-dc-power-conversion/offline-controllers/NCP1396#technical-documentation It lists a SPICE model (called an ORCAD model, but will most

Hi Denys, thanks for sharing, this is a interesting paper that include the basic LLC design topics. Is it possible to find out the example spice file, NCP1396A.asy and NCP1396A.lib?

I'm not a math expert, I'm an engineer but I understand the potential issues with large scale matrix math. LTspice has 3 different integration methods, trap, modified trap and gear. The trap method

It does mean that the control voltage to the YIG VCO is a ramp.? But the error voltage from the doubly balanced mixer (phase detector) might not be a ramp; it might be a steady voltage (after

john23, I'm going to tell this to you again: DO NOT upload your files into various subdirectories within the group's Files section.? Upload into the Temp ( /g/LTspice/files/Temp )

The signal that I desire in PLL is 0V , when my YIG is drifting in one direction that means that my error signa is like a ramp. 0 and then going up(thus making the frequency move in one direction).

Also, as

I? uploaded a fixed version of your file to show you how it's done: rectification-filter_m3_ATC </g/LTspice/files/Temp/rectification-filter_m3_ATC.zip>. I hadn't realised that your

Yes Tony, but I don't know how to integrate these formulas into my diagram. And what is the LOAD command, I can't find any help in LTSpice. -> rectification-filter_m3.asc

FYI - I'm seeing about 0.325 V p-p with your 4500 uF capacitor, so it is not quite large enough to get the ripple under 0.30 V.? The comment on your schematic is incorrect. LTspice is good for doing

It is easy to calculate the (approximate) required capacitor value based on load current and input frequency: C ? Iload/(2*F*Vpp) where: Iload is? DC load current F is the sinusoidal input

Thank you for your help

Merci pour votre aide

OK with the .step command. Modified circuit rectification-filter_m2.asc