On Tue, May 28, 2024 at 12:45 PM, Andy I wrote:

How to do that depends greatly on the frequencies involved.

Could you please explain the frequency dependency for a frequency value of 10 MHz? Also for the C1 choice.

Ethan,

I think you want to seriously think about moving away from AC-coupling the pulse to the 555 with a small time-constant.? It's contributing to this problem.

One thing to keep in mind is that your op-amps and comparators in the simulation are the ideal "UniversalOpAmp2", which is very linear (until it clips) and very idealized.? The fact that its core is linear means it sends few if any "clues" to the timestep control algorithm, to tell it when to slow down (make the Timestep smaller).? As a result, it can miss the timing of the falling edge at U2's output.? By the time it checks in and sees that U2's output is low, the result is a simulated fall-time of about 250 us instead of 20 us.? It's not a huge difference, but that makes the dv/dt too slow to pass through the AC-coupling.

Why did you make C2 smaller?? IIRC, it was 2n2 before and now it's 1n.? It seems as if you pushed it to see when it would fail.? Even the normal signal (fast pulse) is attenuated by C2.

There are likely combinations of settings that can avoid this problem.? Setting TRTOL to 0.01 seems to help.? But it doesn't SOLVE the problem.? If you had used real comparators with transistors, it's likely that this problem would not occur because LTspice would see U2 switching and slow down.? If C2 was larger, the problem probably would go away.

I want to mention that the real circuit might fail to oscillate, depending on power-up.? If U2 starts already high (maybe unlikely that it would, but if it did), the circuit would never oscillate.? That AC-coupling just bothers me.

Andy

Check out Coilcraft for conical and broadband inductors.

?

Sorry - adding a little more to my previous reply.

Regarding this question: "Could you please tell me how to design RF choke (L2)?"

How to physically design it is really off-topic for this group.? But basically you might want to design L2 so that it has a large non-reactive impedance at the RF signal frequency, and at harmonics because of those step recovery diodes that connect to it.

How to do that depends greatly on the frequencies involved.

An ideal inductor is inductive = reactive impedance.? That could be a bad thing, if it resonates with other circuit elements.? To circumvent that, designing the inductor with a lot of RF resistance helps.? Ferrite beads do that.? Some cores for coils have a permeability making them lossy over ranges of frequency, leading to a terminal impedance with a large resistive (real) component without adding DC resistance.

When it's called a "choke", that might mean it has a large |Z| while not being only inductive = reactive.

The figure (5.png) shows R2 in series with L2.? That could help too if L2 does not have enough real (non-reactive) impedance.

Andy

My VCO circuit ran fine yesterday after I changed trtol from 2 to 1, but today it stops early again.? I added ".options trtol=1" to the schematic but that didn't help either. What the heck? I just uploaded the current version named Winer VCO 2.asc. Thanks in advance for any advice.

abid asked, "Could you please tell me how to design RF choke (L2)? Is it just an inductor?"

Yes, a choke is an inductor.

But no, an inductor is never just an inductor.? Real inductors (or coils or chokes) can have all sorts of things going on, including magnetic nonlinearity, RF loss resistance, eddy currents, skin effect, self-resonance, etc. etc.

re: "What should be its value since the paper didn't mention it?"

I suggest asking the paper's author(s) for the answer to that question.? Or do some research into NLTLs.? (Google is your friend, and should help with this.)? This is only a guess, but the inductors might actually be short sections of transmission line such as PCB traces.? If so, each "L" in the figure is really a short t-line, and short t-lines can be represented by (or modeled as) a series L and a shunt C.? They might have blended the C into the varicaps, if they dominate the capacitance.

It is ironic that the figure calls it a "linear NLTL" which I assume means "linear non-linear transmission line".? (I assume that use of the two "linears" refer to different things, one to nonlinear diodes, the other to uniformity along its length?)

re: "Also, what value should I use for bypass capacitor C2 and DC blocking capacitor C1 (not provided in paper)?"

I will pass that back to you.? You should be able to work on figuring those out.? C2 should be large enough to effectively smooth and filter the DC voltage, but not unreasonably large, and you don't want it to become ineffective at signal (RF) frequencies.? C1 should be large enough to pass the input AC voltage.? I don't know the signal's frequency, and that is a huge factor in that choice.

Andy

Thank you so much Andy!

?

I have uploaded another picture (5.png) in this album /g/LTspice/album?id=295221. Could you please tell me how to design RF choke (L2)? Is it just an inductor? What should be its value since the paper didn't mention it?

Also, what value should I use for bypass capacitor C2 and DC blocking capacitor C1 (not provided in paper)? Given, R2 = 50, R3 = 4.6k, L1 = 20nH.

Donald wrote, "Reminds me of one very early lesson I learned in University EE classes, back in the day when researchers were developing new methods of simulation: amplifiers oscillate; oscillators don't."

That often applies to the real circuits, too.

Andy

Hi.
I had to model an old circuit in LTspice24 (needed to recalculate some things) and it didn't work. I had to force TRTOL=1 to make it work. I came to the conclusion that the previous value of TRTOL=1 was fully justified. Previously, when I needed to speed up the counting, I used to set TRTOL=7 or even TRTOL=10. It turns out that now the LTspice guys have decided that users are stupid and cannot increase TRTOL themselves. Some users may have problems because of this. I am very unhappy about this.

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Reminds me of one very early lesson I learned in University EE classes, back in the day when researchers were developing new methods of simulation: amplifiers oscillate; oscillators don't.

Donald.

This group is great, and you folks are the best. Andy nailed it. In Settings trtol was set to 2. I changed it to 1 and now my circuit runs perfectly. A bit of explanation if anyone who cares:

First, I restructured the circuit to buffer the charged cap with an op-amp. before going to the comparator. I also noted on the schematic that the op-amp should have an FET input and the cap should be film. The cap to the 555's trigger input is to ensure that the dump time isn't extended no matter how long the comparator stays low for. And the second transistor Q2 is to ensure that the comparator stays low long enough to fully discharge the cap based on the 555's time. I cleaned that up too.

Thanks again, folks, and especially Andy.

Ethan,

I can tell that your file "Winer VCO.asc" simulates well without any changes on my LTspice 17.0.37.0 (with the default Modified Trap integration method)

abid, I uploaded "Q(V).zip" to the Temp folder, with capacitors using the equation for Q(V) that is in the older (2015) paper.

Andy

I'm not where I can test on 24.0.12.
But it works fine on LTspice 17.0.35.0, with or without uic.

I simply unzipped it and ran the sim.
Then removed uic and ran it again.
worked fine with or without uic

If the 555 must be AC-coupled to the comparator, I wonder if C2 is just to small?

Andy

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On 25/05/2024 23:46, Ethan Winer wrote:

I can't tell if the problem with this voltage controlled oscillator is my circuit or LTspice itself. I'm using the current version (X64): 24.0.12. When I change the .tran length the behavior in LTspice changes, so maybe the experts here can figure it out. I just uploaded the file "Winer VCO.asc" for a voltage controlled oscillator. It charges a capacitor from a constant current source, then when the cap reaches 5 volts a comparator dumps the cap through a 555 timer to start charging again. For some reason when .tran is set for 1 full second it stops oscillating before 0.1 second. But with .tran at 0.1 second it oscillates all the way through. Changing the charging current at voltage source V3 also affects how long it runs before pooping out. If you probe the output of the comparator U2, it fades out slightly early at its final switch rather than switching off suddenly I can't see anything in my circuit that correlates with the time it starts to fade out.

It seems to be to do with the internal time step algorithm. There are several ways to prevent it going wrong:

• Set a maximum time step. Anything <=100u seems to fix it (on both V17.1 and 24.0).
  
• Change to the Alternate Solver.
• Set Trtol=1. This used to be the default with Ver<24.
• Set Reltol=0.0001 (default=0.001).
  

Q2 also seems to have no purpose and the oscillator works fine without it. Its presence very slightly changes the tuning law at higher frequencies.

Again, using uic is no benefit in this analysis. It very rarely is.

--
Regards,
Tony

Hmm.? I am not seeing any of the behaviors you described, but maybe a setting changed, which affects it.

Check your TRTOL setting.? LTspice used TRTOL=1, until version 24 changed it to 2.? If you have increased yours to 7 (which is what other SPICE programs used), it might not work.? That setting is remembered in LTspice so it could be left over from another simulation you did.? You can add ".options trtol=1" to your schematic to change TRTOL for just that simulation while not changing the remembered setting.

If that doesn't help, can you reset all the LTspice settings back to defaults?

TRTOL affects the internal timestep.? If, somehow, the timestep became unusually large, larger than the VCO's expected period for example, then it could stop oscillating.? One remedy is to force a Maximum Timestep that is small compared to the period of the highest frequency.? Actually it should be smaller than the fastest signal anywhere in the circuit, but that would be quite a bit smaller than one period, and it might make the simulation run too slowly.? A properly set TRTOL ought to make that unnecessary.

There might be a problem also with the AC-coupling between comparator U2 and the NE555; and perhaps another with lack of hysteresis at the comparator.? With a relaxed timestep, the apparent dv/dt at the output of the comparator might be insufficient to AC-couple through C2 to the 555.? Does C2 need to be there?

Andy

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I think there s a design fault, but I can't identify it. However, UIC is not your friend (it usually isn't). It works for nearly 0.5 s without UIC.

I can't tell if the problem with this voltage controlled oscillator is my circuit or LTspice itself. I'm using the current version (X64): 24.0.12. When I change the .tran length the behavior in LTspice changes, so maybe the experts here can figure it out. I just uploaded the file "Winer VCO.asc" for a voltage controlled oscillator. It charges a capacitor from a constant current source, then when the cap reaches 5 volts a comparator dumps the cap through a 555 timer to start charging again. For some reason when .tran is set for 1 full second it stops oscillating before 0.1 second. But with .tran at 0.1 second it oscillates all the way through. Changing the charging current at voltage source V3 also affects how long it runs before pooping out. If you probe the output of the comparator U2, it fades out slightly early at its final switch rather than switching off suddenly I can't see anything in my circuit that correlates with the time it starts to fade out.

I can't tell if the problem with this voltage controlled oscillator is my circuit or LTspice itself. I'm using the current version (X64): 24.0.12. When I change the .tran length the behavior in LTspice changes, so maybe the experts here can figure it out. I just uploaded the file "Winer VCO.asc" for a voltage controlled oscillator. It charges a capacitor from a constant current source, then when the cap reaches 5 volts a comparator dumps the cap through a 555 timer to start charging again. For some reason when .tran is set for 1 full second it stops oscillating before 0.1 second. But with .tran at 0.1 second it oscillates all the way through. Changing the charging current at voltage source V3 also affects how long it runs before pooping out. If you probe the output of the comparator U2, it fades out slightly early at its final switch rather than switching off suddenly I can't see anything in my circuit that correlates with the time it starts to fade out.

john23,

The model Tony uploaded comes from the transistor's S-parameters.? S-parameters show the linear behavior of the transistor.? Since it is used in a 675 Watt (DC input) power amp, it is nonlinear.? S-parameters might suffice, but be aware that the S-parameters apply only at one operating point.? If you use the transistor with different conditions (different gate drive or output power), its S-parameters will change, and then the SPICE model does not fit anymore.

Andy